Re: [coreboot] About rs780 CIM

Thanks. And I found the comment /* * Set registers in RS780 and CPU to enable the internal GFX. * Please refer to CIM source code and BKDG. */ from the file Targets/Bonito3a780e/pci/rs780_gfx.c, where is CIM source code? On Tue, Apr 09, 2013 at 12:43:30PM +0200, Paul Menzel wrote: Dear

Re: [coreboot] porting to GA-945GCM

Dear Guangzhe Lee, Am Mittwoch, den 10.04.2013, 13:31 +0800 schrieb CTO of SPCTNC: […] I'm from China. My name is Guangzhe Lee. and I'm new in Coreboot. welcome to coreboot! Could you please tell me, what your first name (also known as given name) is. Is it Guangzhe? My first name is

Re: [coreboot] About rs780 CIM

Dear yili0568, please do not top post but use interleaved style instead [1]. Am Mittwoch, den 10.04.2013, 15:04 +0800 schrieb yili0...@gmail.com: Thanks. And I found the comment /* * Set registers in RS780 and CPU to enable the internal GFX. * Please refer to CIM source code and BKDG. */

Re: [coreboot] About rs780 CIM

On Wed, Apr 10, 2013 at 09:37:34AM +0200, Paul Menzel wrote: Dear yili0568, please do not top post but use interleaved style instead [1]. I'm sorry. Am Mittwoch, den 10.04.2013, 15:04 +0800 schrieb yili0...@gmail.com: Thanks. And I found the comment /* * Set registers in RS780 and

Re: [coreboot] About rs780 CIM

Am Mittwoch, den 10.04.2013, 16:36 +0800 schrieb yili0...@gmail.com: On Wed, Apr 10, 2013 at 09:37:34AM +0200, Paul Menzel wrote: please do not top post but use interleaved style instead [1]. I'm sorry. No problem. Thank you for now following the netiquette! Am Mittwoch, den 10.04.2013,

[coreboot] link trainning of rs780e is x2

Hello: everyone, the gfx configured as 2 x8 slot, after link trained successfully, I printed the width , the value of which is 4. Does it means the link width is x8? from the function dual_port_configuration .. switch (width) { case 1:

Re: [coreboot] cbfstoool: Cppcheck 1.59 warnings with hash 33e83ca

* Paul Menzel paulepan...@users.sourceforge.net [130409 00:51]: Dear coreboot folks, if somebody is bored ;-), here is the output of Cppcheck for cbfstool to fix. :P Since you already started looking into the issue, maybe you can save the rest of us some time by following through with it

Re: [coreboot] porting to GA-945GCM

* CTO of SPCTNC spc...@gmail.com [130410 07:31]: Please help me. - How can I fix the problem. It sounds like you have a RAM init problem (e.g. your RAM is not working) because the chipset (945GC) is slightly different than the other 945 variations that we have supported (just a guess) -

[coreboot] X201 bootblock unlocking

Hello all. On X201 top 192K are locked. Fortunately the original BIOS has a way to update this region. If you extract a X201 image you'll find a lzint compressed file which makes 192K decompressed. It's the update. In it you can simply replace 74f8d1fe (PR0) with 74f8d0ff (harmless address with

Re: [coreboot] coreboot has been accepted for GSoC 2013

Marc Jones wrote: Many students are not familiar with the complexity and issues involved in firmware and bootloaders. Nor with open source processes and tools, unfortunately. :\ If you know any students, tell them about GSoC and promote coreboot! What's the executive sales pitch for a

[coreboot] coreboot: make crossgcc - Failed to download acpica-unix-20121114.tar.gz.

Dear coreboot folks i downloaded the latest source code form coreboot.org , when i tried to build the cross compiler using the command make crossgcc it gives the following error root@test-VirtualBox:~/coreboot# make crossgcc Warning: no suitable GCC for armv7. Welcome to the coreboot cross