Re: [coreboot] Questions on building a Coreboot ROM for the Dell Chromebook 11

hi Marcos, I'm not a Google dev, just a hobbyist, but I've spent a lot of time over the past year working with coreboot for the Haswell ChromeOS devices (mostly the ChromeBoxes) and can offer some answers, inline below. On 5/8/2015 2:38 PM, Marcos Scriven wrote: > I have a Dell Chromebook 11 (G

Re: [coreboot] coreboot fails to build in master tree

On 05/08/2015 08:20 PM, David Hendricks wrote: Hi Timothy, We were unable to replicate the failure you're seeing, however it did appear that there may be an issue with the builder's environment. There were also some patches that appeared to be committed in the wrong order, thus causing a missing

Re: [coreboot] coreboot fails to build in master tree

Hi Timothy, We were unable to replicate the failure you're seeing, however it did appear that there may be an issue with the builder's environment. There were also some patches that appeared to be committed in the wrong order, thus causing a missing header error, but there were no merge conflicts a

[coreboot] coreboot fails to build in master tree

All, Earlier today the master coreboot tree broke; it now fails to build: fmd_scanner.l: In function ‘parse_integer’: fmd_scanner.l:47:25: error: declaration of ‘input’ shadows a global declaration [-Werror=shadow] :1192:16: error: shadowed declaration is here [-Werror=shadow] fmd_scanner.l: I

[coreboot] Questions on building a Coreboot ROM for the Dell Chromebook 11

I have a Dell Chromebook 11 (Google codename 'Wolf') which I'd like to install a custom coreboot ROM on. Although John Lewis provides ROMs here https://johnlewis.ie/custom-chromebook-firmware/rom-download/, I'd rather not use them for a few reasons: 1) It's replacing one 'closed' ROM with another,

Re: [coreboot] [poll] device_t

On Fri, May 8, 2015 at 12:16 PM, Patrick Georgi wrote: > 2015-05-08 17:31 GMT+02:00 Aaron Durbin : >> In romstage *both* struct device and device_t are present but are >> completely different types. It's the romstage, ramstage, and smm >> overlap that is large and extremely annoying to deal with.

Re: [coreboot] [poll] device_t

2015-05-08 17:31 GMT+02:00 Aaron Durbin : > In romstage *both* struct device and device_t are present but are > completely different types. It's the romstage, ramstage, and smm > overlap that is large and extremely annoying to deal with. History time: Until not too long ago, bootblock and romstage

Re: [coreboot] [poll] device_t

On Fri, May 8, 2015 at 8:31 AM Aaron Durbin wrote: > > I personally feel that changing device_t type based on stage makes the > code non-obvious and hard to follow. > > I'd rather we *always* provide simple u32 device_t functions in all > stages while allowing struct device IO functions for use i

Re: [coreboot] [poll] device_t

On Thu, May 7, 2015 at 3:42 PM, Patrick Georgi via coreboot wrote: > 2015-05-07 22:00 GMT+02:00 Stefan Reinauer : >> With our current bootblock concept, it is never going away on x86 (for >> bootblock usage) > Which isn't that much of a problem once we provide separate headers > for x86 bootblock

[coreboot] ASUS KFSN4-DRE Automated Test Failure

The ASUS KFSN4-DRE fails verification as of commit b11be321a895aa70adeaa8cb92fcfcd5dcbd748c The following tests failed: CBMEM_OBJECT_TABLE_TRUNCATED Commits since last successful test: b11be32 build system: use platform specific ar(1) for libverstage 7aafe53 timestamp: fix incremental linking er

[coreboot] coreboot debugging with qemu-x86

Hi, I am trying to debug coreboot with qemu-x86 with the following command - qemu-system-x86 -L . -bios coreboot.rom -nographic I am getting output something like this - http://pastebin.com/Ae2X5sPe (Also pasted below) EAX= EBX= ECX= EDX=0633 ESI= EDI=00

Re: [coreboot] u-boot as coreboot payload on qemu-x86

Hi Ajay, The issue was that qemu-x86 did not support u-boot. Resolved it by picking up latest commits. Regards, Saket Sinha On Wed, May 6, 2015 at 11:26 AM, Ajoy Das wrote: > what is the difficulty u r facing ? > > yes it is suppose to work > > Thanks > Ajoy > > On Tue, May 5, 2015 at 7:39 PM,

Re: [coreboot] AGESA PI for Olivehill+

Hello Kyösti, hello Wim, with AGESA source there is a file buildOpts.c in the mainboard directory. In this file you can overwrite seed values and they will be passed to AGESA build. With binary Pi this file is absent. How is it possible to pass values to binary PI? My AMD support comes from Asc

[coreboot] WG: AGESA PI for Olivehill+

Von: Wolfgang Kamp - datakamp Gesendet: Freitag, 8. Mai 2015 09:34 An: 'Kyösti Mälkki' Betreff: AW: [coreboot] AGESA PI for Olivehill+ I have SPD EEPROM on board. File is checked. But I think required DDR3 seed values are different between memory down star topology and SODIMM DDR3 modules in