Thank you for spkmodem comments, now I'm trying out a more reliable
way - FT232H dongle - to extract the logs from AMD Lenovo G505S. I
plug it into the correct port - USB 2.0 at laptop's right side.
However it doesn't print anything except this short test message:
--- /* Perform a small write. */
Hi Jose,
You wrote:
"My recommended approach is using the original Intel FW with already
included the FD, TXE".
What is "original intel FW" ?
What is FD, TXE ?
After creating coreboot.rom should I always use the original BIOS with
ifdtool to convert rom to bin ?
Thank you,
Zvika
On Wed, Sep
I spoke too soon. It just flat out does not work to have sf100 and 256Mbit
part AFAICT
On Fri, Sep 28, 2018 at 11:19 AM ron minnich wrote:
> Got the fix. I used dpcmd to update the firmware on the FS100 to 5.5.3
>
> Then flashrom can program it with ease.
>
> And, ironically, while dpcmd can
On Thu, Sep 27, 2018 at 10:18 PM Sam Kuper wrote:
>
> On 28/09/2018, Peter Stuge wrote:
> > Youness Alaoui wrote:
> >> avoid any malware writing to the flash
> >
> > Just disallow flash writes by the platform. Allow flash writes only
> > by dedicated hardware (maybe ChromeEC?) which implements a
Got the fix. I used dpcmd to update the firmware on the FS100 to 5.5.3
Then flashrom can program it with ease.
And, ironically, while dpcmd can update the firmware, it still can't flash
the part :-)
ron
--
coreboot mailing list: coreboot@coreboot.org
This issue is sorted out
cpu_microcode_blob.bin matches the ".h" file for microcode
the SoC still fails at this point
msr.lo = (unsigned long)m + sizeof(struct microcode);
msr.hi = 0;
*wrmsr(0x79, msr);*
Any clues?
On Fri, Sep 28, 2018 at 5:28 PM galla rao wrote:
> Hi ,
>
> How does
Hi ,
How does the coreboot picks the cpu microcodes
as a blob or ASCII ?
Tried both option GENERATE FROM TREE and INCLUDE EXTERNAL HEADER
In Memory it appears it picks the ASCII file, but not a blob
intel/cpu/baytrail/microcode/M0130679901.h
0x0001, /* Header Version */
0x0901, /*
They were made on the day that I marked the wiki read-only, after I marked
it read-only. After that, nothing changed (see
https://coreboot.org/index.php?title=Special:RecentChanges=10=3
)
So yes, they're as new as the wiki can get and they should all be identical
(modulo potentially export
Yes, kernel can be start at any address.
You can refer to BBL implementation : https://github.com/riscv/riscv-pk
BBL converts vmlinux to binary and inserts it into the section named .payload
which is one section of BBL.
Because the size of the BBL cannot be known before compiling and linking,
On 09/15/2018 10:11 AM, Patrick Georgi wrote:
> Am Sa., 15. Sep. 2018 um 16:10 Uhr schrieb taii...@gmx.com > :
>
>> Would this be the best way to do it? [...]
>
> wget -r -k -np -p -l 0 http://coreboot.com/wiki
>
> Maybe not. See https://www.coreboot.org/wikidump/ for more suitable formats.
>
I have a coreboot-libre D16 and it works fine with xen - no errors and I
haven't even embedded microcode in coreboot (req for my 43xx/63xx) I
instead do an early update from initramfs.
I suggest obtaining a null modem serial cable and a real serial pci-e
card or expresscard device (nothing
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