[coreboot] Re: Intel sVID controller and SVID bus.

Intel CPUs typically drive SVID-enabled PMICs using an internal small core (at least Core m and Core i parts). In any case, the peripherals on SVID bus have addresses that sometimes are assigned via bootstrap pins. Your Denverton design probably has a TI and ST Micro PMICs connected to SVID. If

[coreboot] Re: Locking coreboot against internal flashing

Would it make the most sense to put locking option in coreboot's board-specific code, since the method varies between boards? Could a common ACPI call for it be provided that could be called by a payload or OS later if it's present? -Matt On Sun, Feb 17, 2019 at 8:48 PM Frank Beuth wrote: >

[coreboot] Re: Intel sVID controller and SVID bus.

Hi, Slow performance might be due to thermal throttling, Can you please check prochot# signal? It should be high(voltage equal to power rail to which it's pulled up to) In Linux, you can use powertop program to monitor CPU frequency, CPU C-states. Under some load, CPU will utilise max frequency.

[coreboot] Re: RAM without SPD

Hi Michal, Thank you very much for your help. Best regards, Zvika On Thu, Feb 21, 2019 at 10:17 AM Michal Zygowski wrote: > > On 20.02.2019 22:14, Zvi Vered wrote: > > Hi Michal, > > Hi Zvika, > > > Your detailed answer is highly appreciated ! > > The output I got on the console is: > ... >

[coreboot] Intel sVID controller and SVID bus.

On the motherboard developed by our company (intel atom denverton 3538), there is a low performance of the processor and memory. When trying to monitor the exchange of the SVID bus lines with the oscilloscope (SVID_CLK, SVID_DATA and SVID_ALERT), no activity was noticed. Circuit design is