> True, however we can still set expectation even if there is no way to enforce
> it. This would be more of a social norm than a hard requirement, but it does
> help to know that if you are e.g. pushing an entire board into coreboot, that
> to keep it in tree you are expected to do amount of
- Original Message -
> From: "Julius Werner"
> To: "Timothy Pearson"
> Cc: "Martin Roth" , "Peter Stuge" ,
> "coreboot"
> Sent: Thursday, May 2, 2019 5:23:58 PM
> Subject: Re: [coreboot] Re: What maintenance is expected from coreboot
> developers & companies
> I don't think as an
I don't think as an open-source project we can really set hard
expectations of what a contributor does after their patch is landed,
regardless of whether it's an individual or a company. We don't make
our contributors sign contracts, after all. Any work on coreboot by
anyone is best effort, and
I would suggest the same industry standard maintenance period that would
normally apply to a commercial, closed source product. For instance, consumer
hardware might only receive a year or two of support from initial release, but
an embedded system might be more typically see 3-5 years or
Thanks Peter,
Is there a time limit that you think is appropriate to request
maintenance for?
Obviously it's not reasonable to request that they maintain it
forever, but is 2 years after the initial push reasonable? 3 years?
What level of maintenance would be expected? Would we just
Hello Nico, thank!
If I understand correctly, when setting up a FSP with memory down, FSP does
not read the SPD, but waits for the setting as a function parameter.
If I set memory as DIMM in the FSP, then the FSP will read the SPD from the
specified SMBUS address (A0, A2).
I'm right?
Hello Alexey,
On 02.05.19 10:20, Alexey Borovikov wrote:
> How to configure the board with soldered memory where spd?
> Is there any difference when using a memory controller with soldered memory
> with spd and DIMM?
this really depends on your board design. If the board with SPD follows
the
Thanks.
But it works if the memory down on board and board not have chip SPD. However,
if the board has a SPD, this code does not work.
From: Ranga Rao
Sent: Thursday, May 02, 2019 12:54 PM
To: Alexey Borovikov ; coreboot@coreboot.org
Subject: RE: [coreboot] FSP 1.0: How to configure soldered
On 02.05.19 08:10, Martin Kepplinger wrote:
> On 25.04.19 12:23, Patrick Georgi via coreboot wrote:
>> There was some recent cleanup on console.h includes that makes printk
>> only visible where we thought it was needed.
>> A change to add an include for console/console.h to resolve the issue
>>
Hi Alexey,
For memory down configuration ensure below are enabled/filled in FSP
When a DIMM is having its SPD, the smbus reads the SPD and configures the DIMM
channels
For Memory down below changes are expected
1. UpdData->MemoryDownEnable is enabled
2)
MEMORY_DOWN_DATA
There are two boards Intel Atom E3825 with soldered memory. One board with spd,
the other without spd. For a board where there is no spd, after configure the
correct memory settings in the fsp, I get a working memory controller. For a
board with spd, the fsp configurator does not allow to
On 25.04.19 12:23, Patrick Georgi via coreboot wrote:
> There was some recent cleanup on console.h includes that makes printk
> only visible where we thought it was needed.
> A change to add an include for console/console.h to resolve the issue
> here. Cc'ing Elyes since that's his effort.
>
> As
12 matches
Mail list logo
