coreboot leadership meeting notes are now public:
https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgKjeDQ/edit#heading=h.j7tqwova2640
Anyone interested in joining the leadership meetings in the future can
check the calendar on the coreboot website for call-in information.
On Wed, May 22, 2019 at 6:14 PM Дмитрий Понаморев wrote:
>
> The controversial decision but the console output is not connected directly
> to the processor but to the superio Nuvoton.
> I did not find any settings to enable LPC (LPC_EN) for the Atom C2000 to.
> In
Usually LPC_CLKOUTx signals are programmed to native function, so that
controller inside SOC generates the clock required. FSP code for LPC is stable
enough to configure LPC controller registers to generate clocks. Did you verify
configuration of all LPC gpios? They should be programmed to
The controversial decision but the console output is not connected directly
to the processor but to the superio Nuvoton.
I did not find any settings to enable LPC (LPC_EN) for the Atom C2000 to.
In atom-c2000-microserver-datasheet-334978.pdf I found register LPCC (LPC
control register).
This
Hi everybody,
thanks to all contributors who voted on the issues brought up by
the coreboot leadership team. We had 119 eligible voters and three
questions.
I'll now summarize the results:
# How to handle copyright notices
https://civs.cs.cornell.edu/cgi-bin/results.pl?id=E_9e4f5ea789b9ceb9
59
> did the ASUS KFSN4-DRE ever receive family 15h support, in addition to 10h?
> or was that only the KGPE boards?
When I go to a "./src/mainboard/asus/kgpe-d16" or
"./src/mainboard/asus/kcma-d8" and do this search:
find . -type f -print0 | xargs -0 grep -n "15h"
- there are multiple matches at
What's good about the AtomBIOS ROMs: you can use AtomDis tool ( [1] /
[2] ) to get some idea - about what's inside them and what they're
doing. Run "make" to compile it and then use a command like ./atomdis
pci1002,990b.rom F > pci1002,990b.rom.dis . I'm sharing my
disassemblies as .dis files at
Thanks, I was actually able to get it up and running on coreboot 4.9. The main
issue was that i am on fedora, and CONFIG_STRICT_DEVMEM is enabled by default.
adding GRUB_CMDLINE_LINUX"iomem=relaxed" while also adding the proper defines
in gpio.c and gpio_group.c seemed to fix the issue. my
Hi Justin,
Ensure the GPIO’s for the south bridge you are looking for kaby lake 7280
are available in coreboot\util\inteltool\gpio.c
CM238 is a skylake chipset ->
https://en.wikipedia.org/wiki/List_of_Intel_chipsets
Have you tried inteltool -g -G?
Regards
Ranga
From: Justin Dong-Il Lee
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