On Tue, Jan 19, 2021 at 9:17 AM Tim Wawrzynczak via coreboot
wrote:
>
>
>
> On Tue, Jan 19, 2021 at 9:27 AM Michał Żygowski
> wrote:
>>
>>
>> On 1/19/21 5:10 PM, Tim Wawrzynczak via coreboot wrote:
>> > Dear Michał,
>> >
>> > Do you have a config for us to look at for your board? Are you
>> > us
On Tue, Jan 19, 2021 at 9:27 AM Michał Żygowski
wrote:
>
> On 1/19/21 5:10 PM, Tim Wawrzynczak via coreboot wrote:
> > Dear Michał,
> >
> > Do you have a config for us to look at for your board? Are you
> > using INTEL_CAR_NEM_ENHANCED ?
>
> Hi Tim,
>
> Sure, see attached, yes INTEL_CAR_NEM_ENHAN
On 1/19/21 5:10 PM, Tim Wawrzynczak via coreboot wrote:
> Dear Michał,
>
> Do you have a config for us to look at for your board? Are you
> using INTEL_CAR_NEM_ENHANCED ?
Hi Tim,
Sure, see attached, yes INTEL_CAR_NEM_ENHANCED is selected.
>
> Based on the post code you observed last, I might gue
Dear Michał,
Do you have a config for us to look at for your board? Are you
using INTEL_CAR_NEM_ENHANCED ?
Based on the post code you observed last, I might guess that you overfilled
the cache when doing the cache fill
operation, e.g. the next few lines in cache_as_ram.S after post-code 0x26;
doi
Dear coreboot community,
I have a Tiger Lake UP3 RVP and I try to build a working coreboot on it,
however facing an early stuck during CAR setup. Tried different approaches:
- native coreboot's CAR setup - the last seen post code is 0x26
- FSP-T CAR setup - the last seen post code is 0x7F (which
Hi
Is there any basic code in coreboot tree for recent AMD APUs ?
Specifically Bristol Ridge FX-9830P is of my interest, how much work
is needed to get laptop booting it?
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