[coreboot] Fwd: Denverton: NVMe not detected when serial console logs are disabled

Hi Paul, When logs are (almost) disabled the error isn't shown, so if I add the delay with logs disabled the log output will have almost no difference at all. Following are the logs, including a log with Coreboot debug enabled + no delay. For all logs FSP loglevel is set to NoDebug: -

[coreboot] Re: A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

Hi Sumo, > ... It’s also possible (but not confirmed) that for a particular SKU > (other than 16-core SKUs), it might not be consistent between parts > I can confirm this, I have two C3558 SoC's with first core different APID > ID's... > I can confirm it too for C3338, C3538. Do you think I

[coreboot] Re: A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

Hi Jay, > ... It’s also possible (but not confirmed) that for a particular SKU (other than 16-core SKUs), it might not be consistent between parts I can confirm this, I have two C3558 SoC's with first core different APID ID's... Do you think I can submit my patch (see previous discussions) or

[coreboot] Re: Denverton: NVMe not detected when serial console logs are disabled

Dear Sumo, Am 16.08.21 um 18:38 schrieb Sumo: The NVMe is not detected when serial console logs are disabled, I mean by setting both Coreboot log_level=Error (or less) and FSP PcdFspDebugPrintErrorLevel=NoDebug. Looks like the enumeration fails then further on the device is not listed in the

[coreboot] Re: A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

The solution to this problem has already been discussed here. You just need to replace in the file devicetree.cb "lapic 4" to "lapic 0xbeef". *device cpu_cluster 0 on#device lapic 4 on enddevice lapic 0xbeef on end #NOTE: correct Local APIC ID is set in in dev_enumerate() end* This

[coreboot] Re: A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

Unfortunately, for the Denverton SoC (C3000 series), the APIC ID of the first core is not always the same. For 16-core SKUs, it’s always 0, but for SKUs with a lower number of cores, it may be a different number. It’s also possible (but not confirmed) that for a particular SKU (other than

[coreboot] Denverton: NVMe not detected when serial console logs are disabled

Hi, The NVMe is not detected when serial console logs are disabled, I mean by setting both Coreboot log_level=Error (or less) and FSP PcdFspDebugPrintErrorLevel=NoDebug. Looks like the enumeration fails then further on the device is not listed in the UEFI FW (same issue shown in either

[coreboot] Re: A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

Hi, > have you tried omitting the `device lapic` line from the devicetree? I have tested this, in this case Linux shows only one processor core. Therefore the 'device lapic' line is really needed... I can submit that Local APIC Fixup patch to gerrit but I'm not sure if this is really the best

[coreboot] Re: Build for F2A85-M Foobared, any ideas?

On 16/8/21 8:43 pm, Paul Menzel wrote: It’s in the path name or logs in the directory I referenced: 4.13-917-g192177d34d refers to commit hash 192177d34d.         I've tried both hash's refrencing both sucessfull builds for F2A85-M board. I just get:         error: pathspec '192177d34d' did

[coreboot] Re: Build for F2A85-M Foobared, any ideas?

Dear Keith, Am 16.08.21 um 12:39 schrieb Keith Emery: I went one further and just deleted the whole working directory, re-cloned coreboot and built using that exact configuration. All to little avail. Please do not leave the other questions/requests unanswered. How do I go about finding

[coreboot] Re: Build for F2A85-M Foobared, any ideas?

Dear Keith, Am 16.08.21 um 09:16 schrieb Keith Emery: coreboot-4.14-1405-gad08265740-dirty Sun Aug 15 07:12:41 UTC 2021 The dirty flag suggests, you have local changes. Please paste the output of `git status` and `git diff`. Also, please attach `defconfig` generated by `make

[coreboot] Build for F2A85-M Foobared, any ideas?

coreboot-4.14-1405-gad08265740-dirty Sun Aug 15 07:12:41 UTC 2021 bootblock starting (log level: 7)... CBFS: Found 'fallback/romstage' @0x30e00 size 0x4c910 in mcache @0x00034f7c BS: bootblock times (exec / console): total (unknown) / 12 ms coreboot-4.14-1405-gad08265740-dirty Sun Aug 15