[coreboot] Re: A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

x - updating in devicetree\n", > > bsp_lapicid); > > dev->path.apic.apic_id = bsp_lapicid; > > } else { > > break; > > }; > > }; > > }; > > }; > > ….. > > > > > > *From:*

[coreboot] Re: A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

rmed) that for a particular SKU (other than 16-core >> SKUs), it might not be consistent between parts. The solution is to >> basically ignore the value in devicetree and use the actual APIC ID from >> the first core. >> >> >> >> - Jay >> >> >> >&g

[coreboot] Re: A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

devicetree and use the actual APIC ID from > the first core. > > > > - Jay > > > > *From:* Sumo [mailto:kingsu...@gmail.com] > *Sent:* Monday, August 16, 2021 9:15 AM > *To:* Nico Huber > *Cc:* Дмитрий Понаморев; Coreboot > *Subject:* [coreboot] Re:

[coreboot] Re: [coreboot-gerrit] Change in coreboot[master]: Add Kyösti Mälkki patch files:

Abandon all? I abandoned 4 last commit... вт, 10 дек. 2019 г. в 16:47, Дмитрий Понаморев (Code Review) < ger...@coreboot.org>: > Дмитрий Понаморев *abandoned* this change. > > View Change <https://review.coreboot.org/c/coreboot/+/37636> > Abandoned > > To vie

[coreboot] Re: How to enable the SMBus0 in coreboot for Intel Atom C2000?

Unfortunately, FITs does not have any settings for SMBus enable/disable and so on. In general, this program for Edisonville_Rangeley is very poor settings. Thanks for youre advice Kyösti! I add files with logs. I tried to play with the enable_smbus() function but without result. Rather, the

[coreboot] Re: How to add NUVOTON NCT6776F support with serial port logic enabled ???

ср, 22 мая 2019 г. в 21:46, Kyösti Mälkki : > On Wed, May 22, 2019 at 6:14 PM Дмитрий Понаморев > wrote: > > > > The controversial decision but the console output is not connected > directly to the processor but to the superio Nuvoton. > > I did not find any settings

[coreboot] Re: How to add NUVOTON NCT6776F support with serial port logic enabled ???

The controversial decision but the console output is not connected directly to the processor but to the superio Nuvoton. I did not find any settings to enable LPC (LPC_EN) for the Atom C2000 to. In atom-c2000-microserver-datasheet-334978.pdf I found register LPCC (LPC control register). This

[coreboot] Atom Denverton processor and memory are very slow.

The processor and memory are very slow. Compiling the ixgbe network card driver takes 10 minutes. The maximum read speed of DDR4 2133 SODIMM is 742 MB / sec. Custom motherboard with Atom Denverton C3538 processor, quad cores 2.1 GHz. SODIMM module: Crucial DDR4 8Gb 2400MHz CT8G4SFS824A. BIOS: