[coreboot] Have a anyidea? that change the serial number of DMI?

Dear Sir. Currently, I was successed the read a serial number, and product name useded the DMI, in kernel space and user space. - kernel space. use the "dmi_get_system_info()" - user space use the "dmidecode" - coreboot space I don't know any soultion. READ is OK. But, i want

[coreboot] How to enable ttyS0 on my board?

Dear Sir. My own board is based on ADI SG-2440. SG-2440 schematic is only connect(enable) the (UART1_RXD, UART1_TXD) to serial console port. So, only can use the "ttyS1" on kernel. But i want to use the "ttyS0". My board's schematic is a connect the uart0(UART0_RXD, UART0_TXD) and

Re: [coreboot] How to extract fsp.bin from image?

Thank you. It is very useful to me. 2017-01-26 오전 1:45에 Andy Knowles 이(가) 쓴 글: Hi, Use the cbfstool, like so: build/util/cbfstool/cbfstool build/coreboot.rom extract -n fsp.bin -f fsp.bin Good luck! Andy *From:*coreboot [mailto:coreboot-boun...@coreboot.org] *On Behalf Of *???

[coreboot] How to extract fsp.bin from image?

Dear Sir. My Purpose isextract *"Intel fsp.bin"* from bios image. *_First_*, (I was know that get possible "Intel fsp.bin" from Intel website. and already download It is.) This time i have a some bios image. This one is _"ADI_RCCVE-01.00.00.08.rom"_. It is get from ADI. Another one is

[coreboot] How to en/disable PCIe root port?

Dear Sir. Happy new year. My board is use the rangeley C2358 SoC. C2358 have a 4 PCIe root port. After kernel boot, i try to check the number of PCIe port that use the "lspci" command. but i can see just 2 port on my board. Result is see below. $ > lspci 00:00.0 Host bridge: Intel

[coreboot] Any one have a experence the coreboot with u-boot?

Dear Sir. My env is see below. board : Intel rangeley MOHON PEAK.(CPU is C2358) I was success boot coreboot + SeaBIOS. This time, I'm try to boot coreboot + u-boot(16.05). But u-boot is every time fail. log is see below. U-Boot 2016.05-rc3 (Nov 28 2016 - 17:04:31 +0900) CPU:

[coreboot] Anyone have a experence the u-boot on coreboot?(Rangeley platform)

Dear Sir. My ENV is see below. CPU : Rangeley C2358(Based on ADI board) Curently, I'm try to use the u-boot(2016.05) but have a "boot fail". log is see below. U-Boot 2016.05-rc3 (Nov 23 2016 - 16:42:44 +0900) CPU: x86_64, vendor Intel, device 406d8h DRAM: 4 GiB

[coreboot] How to read/write the spi flash on SeaBIOS?

Dear Sir. I want to read/write some data to spi flash on SeaBIOS. But i can't found some code or starting point. Do you have a IDEA? If you have a idea or experence, please advise to me. Thank you. -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] How to read the gpio status?

. 2016-07-19 오후 6:42에 Zoran Stojsavljevic 이(가) 쓴 글: Hello 김유석, I did not understand (very imporatnt question): why at all you do need SW I2C (bit-banging I2C) in Coreboot romstage? Maybe you can move your I2C operation later, in ramstage?! Isn't romstage just to do very quick boot and pass

Re: [coreboot] How to read the gpio status?

IO_SC_GP_LVL); Please, always remember the I/O data value you outl() into some heap global variable (which will always retain the latest outl() data value). If you need it back, read this variable. Best Regards, Zoran On Mon, Jul 18, 2016 at 7:20 AM, 김유석 <poplin...@gmail.com <mailto:po

Re: [coreboot] How to read the gpio status?

Dear Sir. The SC_GP_LVL is a 32bit register and I always read 32bit read. Thank you. 2016-07-14 오전 7:00에 Stefan Reinauer 이(가) 쓴 글: * �?�?��?? [160713 06:39]: When write 0x7000 write to SC_GP_LVL, Can read the 0x00 from SC_GP_LVL. everytime. Are you by any chance

[coreboot] How to read the gpio status?

Dear Sir. I want to control the GPIO pin that pin number is 12, 13, 14 DataSheet(P 1909) and coreboot source code(src/southbridge/intel/fsp_rangeley/gpio.c, gpio.h) is said to me that "It is very easy" If i want to set the HIGH to 12, 13, 14 Just setup the some register, is see below.

Re: [coreboot] How can extract descriptor.bin from bios image?

Dear Sir. Thank's your advise. It is very useful to me. My work log is see below. poplinux@raw rangeley $ > ./tools/ifdtool -x ./oem_dumped.bin File ./oem_dumped.bin is 8388608 bytes Flash Region 0 (Flash Descriptor): - Flash Region 1 (BIOS): 0001 - 007f

[coreboot] The GbE is not activated on my Board.

Dear Sir. My ENV EVB : ADI SG-2440 source : official coreboot FSP : intel FSP 4.0 I was successfully build-up the coreboot and successfully boot-up my EVB. But My EVB's GbE is not activated(not running.) So, I was try to boot using the original OEM bios(from ADI). *This image is

[coreboot] How can extract descriptor.bin from bios image?

Dear Sir. My EVB is ADI SG-2440 and mohon peak CRB. This time, My coreboot image are not running GbE. Another guy are said to me that "Must add a descriptor.bin to coreboot.img". And I was found the descriptor.bin from original bios image. See below. * poplinux@raw rangeley $ >

[coreboot] Not running GbE interface.

Dear Sir. My EVB is Rangeley Mohon peak. I was successfuly build and boot the coreboot on my EVB. But, not running the GbE interface. So, I was try to find the mailing list . and Got a some threads. *1. **Message for **G**bE(**This is **perfectly same **that my issue**)*

Re: [coreboot] What purpose the "mrc.cache"?

download it, along with the FSP documentation and the Binary Configuration Tool, from Intel's website: http://intel.com/fsp Martin On Tue, May 31, 2016 at 10:38 PM, 김유석 책임연구원 <kay@hansol.com> wrote: Dear Sir. My ENV. Platform : intel atom rangeley mohon peak CRB(C2358) This tim

[coreboot] What purpose the "mrc.cache"?

Dear Sir. My ENV. Platform : intel atom rangeley mohon peak CRB(C2358) This time, I'm try to study for MRC(Memory Reference Code). But, I'm can not found a some example code on coreboot source tree.(rangely) Anyway, I'm get a some hint on last image. Performing operation on

[coreboot] How to change config of SDRAM of intel mohonpeak EVB on coreboot?

Dear Sir. My own product must need a change the value(config) of sdram. Such as size, speed, and etc. So, I'm try to search and study the coreboot source code, and found out the "vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h" This header are contained the some structure for

Re: [coreboot] SeaBios serial(RX) is not running.

Dear Sir. Thank's your work. Enable the bi-direction serial console is done. 2016-05-20 오후 8:36에 Kyösti Mälkki 이(가) 쓴 글: On Tue, May 17, 2016 at 10:46 PM, Martin Roth > wrote: Hi, If you want bi-directional serial port in

[coreboot] How to change the Core input voltage setting?

Dear Sir. My HW enginner required to me. that Change the setting of "Core input voltage". But, I don't know everything this one. Because x86 platform is first time of my develop life. Anyway, I'm try to find the something on coreboot source code. But, still unknow. So, I need a start

[coreboot] How to control the GPIO on x86 rangely?

Dear Sir. My platform is intel rangely. I'm must contol the GPIO pins, But i'm can't found the example code on coreboot source tree. Could you show me the example code to control GPIO? Thank you. -- coreboot mailing list: coreboot@coreboot.org

[coreboot] SeaBios serial(RX) is not running.

Dear Sir. Thank's your advise. everytime. *Finially*, I was succsss the boot using coreboot. But I have a *little problem.* _*I'm can't typing throuth the serial.*_ My x86 BOX is only support serial console. So, Serial console is very important. *But **t**he **Sea**Bios is **Serial

Re: [coreboot] bootfail on my Mohon Peak CRB.

o generate coreboot image.* On Thu, Feb 4, 2016 at 5:19 AM, 김유석 <poplin...@gmail.com <mailto:poplin...@gmail.com>> wrote: Dear Martin. Thank's your advise. I'm use the serial consol port. but can't see any message. Thank you. 2016-02-02 오후 9:18에 Martin Roth 이(

Re: [coreboot] bootfail on my Mohon Peak CRB.

e instruction of FSP integration guide. * Mainboa**rd* Mainboard vendor (*Intel*) ---> Mainboard model (*Mohon Peak CRB*) ---> [ ] Configure defaults for the Intel FSP package ROM chip size (2048 KB (2 MB)) ---> (0x0020) Size of CBFS filesystem in ROM

Re: [coreboot] bootfail on my Mohon Peak CRB.

, 2016 at 00:41 김유석 <poplin...@gmail.com <mailto:poplin...@gmail.com>> wrote: Dear sir. My ENV is see below. *EVB : Intel rangeley Mohon Peak CRB* This time, I was download the coreboot from git. poplinux@raw work $ > git clone http://review.coreboot.o

[coreboot] bootfail on my Mohon Peak CRB.

Dear sir. My ENV is see below. *EVB : Intel rangeley Mohon Peak CRB* This time, I was download the coreboot from git. poplinux@raw work $ > git clone http://review.coreboot.org/coreboot.git ./ poplinux@raw work $ > cd coreboot poplinux@raw coreboot $ > git submodule update --init --checkout