Has anyone here been able to produce a Coreboot image that contains tint?
It won't compile without a lot of tinkering and uses a really old version.
--
David Griffith
d...@661.org
A: Because it fouls the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top
s
nothing. Taking the exact same .config and setting it for QEMU, coreinfo
works, but selecting nvramcui causes "Could not find coreboot option
table" to be printed.
--
David Griffith
d...@661.org
A: Because it fouls the order in which people normally read text.
Q: Why is top-post
On Tue, 24 May 2016, David Griffith wrote:
On Mon, 23 May 2016, David Griffith wrote:
I'm experimenting with a Thinkpad T60p, specifically getting something
working that includes PXE and secondary payloads. Apparently the default
CBFS size of 0x4 is too small because the build process
On Mon, 23 May 2016, David Griffith wrote:
I'm experimenting with a Thinkpad T60p, specifically getting something
working that includes PXE and secondary payloads. Apparently the default
CBFS size of 0x4 is too small because the build process complains it
can't add ipxe.rom and guesses
-responsive. So, I guess that was a
wrong value.
So, what's a safe value for the CBFS size that will allow me to add PXE
and some other secondary payloads?
--
David Griffith
d...@661.org
A: Because it fouls the order in which people normally read text.
Q: Why is top-posting such a bad thing
can be done with a Sparc machine's OpenBoot environment.
[3] If you're asking if it provides legacy BIOS compatibility, then no.
[4] http://www.openfirmware.info/
--
David Griffith
d...@661.org
A: Because it fouls the order in which people normally read text.
Q: Why is top-posting such a bad
On Fri, 20 May 2016, David Griffith wrote:
On Thu, 19 May 2016, Martin Roth wrote:
-coreboot mailing list
Everyone with a coreboot gerrit account automatically has the rights
to push, but you may need to configure some things.
Sorry, that was supposed to be private.
--
David Griffith
d
g symbol fully
#38: FILE: payloads/external/OpenBIOS/Kconfig:12:
+config OPENBIOS_MASTER
total: 0 errors, 2 warnings, 117 lines checked
===end quote===
Where should these paragraphs go? Basically I just copied and adapted
what I found in payloads/external/SeaBIOS.
--
David Griffith
d...
PENBIOS_MASTER) \
CONFIG_OPENBIOS_STABLE=$(CONFIG_OPENBIOS_STABLE) \
CONFIG_OPENBIOS_REVISION=$(CONFIG_OPENBIOS_REVISION) \
CONFIG_OPENBIOS_REVISION_ID=$(CONFIG_OPENBIOS_REVISION_ID) \
MFLAGS= MAKEFLAGS=
That did the trick. Now I need 'Push' rights.
--
David Gri
installed.
--
David Griffith
d...@661.org
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https://www.coreboot.org/mailman/listinfo/coreboot
/openbios/ and typing "make". What am I doing
wrong?
Here's the contents of payloads/external/OpenBIOS:
http://pastebin.com/9DKJGbyc
--
David Griffith
d...@661.org
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have been removed from the inner chassis.
--
David Griffith
d...@661.org
A: Because it fouls the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing in e-mail?
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https
On Sun, 15 May 2016, Alexander Couzens wrote:
On Sat, 14 May 2016 20:26:08 -0700
David Griffith <d...@661.org> wrote:
Is there any interest in having the Coreboot build process downliad
and build OpenBIOS in the same fashion as SeaBIOS is now?
hi david,
I like it. It would be nice
Is there any interest in having the Coreboot build process downliad and build
OpenBIOS in the same fashion as SeaBIOS is now?
--
David Griffith
d...@661.org
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On Thu, 12 May 2016, Peter Stuge wrote:
David Griffith wrote:
lenovobios_firstflash and lenovobios_secondflash scripts
Please do not confuse coreboot with libreboot. Instructions for/about
libreboot are specific to that project, and nothing that the coreboot
community can support you
i686)
flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK.
Found chipset "Intel ICH7M".
Enabling flash write... WARNING: SPI Configuration Lockdown activated.
OK.
No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found
automatically.
--
David Griffith
d...@661.org
A: Because it fouls the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing in e-mail?
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I narrowed down my flailing from last night to the fact that FILO itself
at the STABLE branch just will not build. The master branch, however,
will. Perhaps is it time to make a new stable branch?
--
David Griffith
d...@661.org
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http
: [0x0010, 0x00124000)
Post relocation: addr: 0x000e5fac memsz: 0x0001a054
filesz: 0xd0e2
using LZMA
lzma: Decoding error = 1
Boot failed
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David Griffith
d...@661.org
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in
there for nVidia SLI. Earlier chipsets don't do SLI. Look here:
http://blogs.nvidia.com/2011/04/you-asked-for-it-you-got-it-sli-for-amd/
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David Griffith
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which
nVidia's drivers look for before enabling SLI.
I see. So, what does this mean for people who want to run a pair of
nVidea boards on a coreboot board in SLI mode?
--
David Griffith
d...@661.org
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On Thu, 19 Jul 2012, Mark Nelson wrote:
On 19/07/12 11:06, David Griffith wrote:
On Thu, 19 Jul 2012, Mark Nelson wrote:
Actually no, SLI support isn't anything to do with the actual chipset
hardware (provided the chipset has the required number of PCI Express
lanes and physical slots
Would it be worthwhile, at least as an learning experience, to port
Coreboot to the Thinkpad T42?
--
David Griffith
d...@661.org
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On Sun, 15 Jul 2012, Idwer Vollering wrote:
2012/7/15 David Griffith d...@661.org:
Would it be worthwhile, at least as an learning experience, to port Coreboot
to the Thinkpad T42?
My advice is to make i855 work on a desktop machine first.
lspci of a thinkpad t42:
http
Would someone please point out where I can get documentation on the AMD
990FX / SB950 north and south bridges? The 800 series stuff is at
support.amd.com, but not these.
--
David Griffith
d...@661.org
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board should be relatively safe because the BIOS
lives in a socketed PLCC. I can't seem to figure out what sort of package
the firmware in the newer one lives in. None of the photos I've found of
it seem to have good enough resolution to tell. Can I get some help here?
--
David Griffith
d
On Fri, 13 Jul 2012, Oliver Schinagl wrote:
On 13-07-12 12:14, David Griffith wrote:
I have an old motherboard which I'd like to experiment on and have my
eyes on a bleeding-edge board. The old one is a Shuttle AN35N Ultra
(socket 1). The new one is an MSI 990FXA-GD80V2 (socket AM3
On Fri, 13 Jul 2012, Oliver Schinagl wrote:
On 13-07-12 13:27, David Griffith wrote:
That looks really interesting. I wonder how much those are going for on ebay.
I also have a HP N36L/N40L microserver that I would love to see coreboot
running on. But since the bios is a SOIC8 i've been
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