On Thu, 2021-11-11 at 16:43 +0100, Julian Stecklina wrote:
> On Thu, 2021-11-11 at 15:21 +0100, Nico Huber wrote:
> > this wouldn't be correct as QEMU doesn't emulate SPI, IIRC. However,
> > selecting BOOT_DEVICE_MEMORY_MAPPED directly would reflect reality. Not
> >
On Thu, 2021-11-11 at 15:21 +0100, Nico Huber wrote:
> Hi,
>
> On 11.11.21 14:05, Julian Stecklina wrote:
> > with the following patch, the Qemu coreboot image indeed does not write to
> > ROM
> > anymore.
> >
> > The question is whether this is beh
BOOT_DEVICE_NOT_SPI_FLASH
+ select BOOT_DEVICE_SPI_FLASH
Julian
On Thu, 2021-11-11 at 12:20 +0100, Julian Stecklina wrote:
> Hi Nico,
>
> On Wed, 2021-11-10 at 10:54 +0100, Nico Huber wrote:
> > >
> > > AIUI, this "hacky way" should be taken, so cbfs_lo
Hi Nico,
On Wed, 2021-11-10 at 10:54 +0100, Nico Huber wrote:
> >
> > AIUI, this "hacky way" should be taken, so cbfs_load_and_decompress()
> > would never be called. First, I'd check if the path is tried, i.e.
> > check the .config file if these are set to `y`:
> >
> > * CONFIG_NO_XIP_EARLY_STA
Hi Patrick,
On Tue, 2021-11-09 at 17:43 +, Patrick Georgi via coreboot wrote:
>
> Is there any particular concern with having coreboot in that memory region on
> your platform that makes you ask this or is this just some general curiosity?
Thanks for confirming that we are not doing anything
Hi!
I have a bit of a newbie question. We're using Coreboot in VMs in our custom
virtualization stack for x86. We are mapping the whole Coreboot image into guest
physical memory so its end coincides with 4G. This makes Coreboot's reset vector
entry point line up with where the hardware wants to st
On Tue, 2021-10-05 at 09:29 +0300, Kyösti Mälkki wrote:
> On Mon, Oct 4, 2021 at 8:12 PM Julian Stecklina
> wrote:
> >
> > But it looks like the workaround was just carried forward with no discussion
> > of
> > whether it's still necessary or what it
The X86_GOOD_APIC was set in the past in a few configs. You can find them via:
git log -S GOOD_APIC --source --all
The define itself was finally removed in:
commit fc57d6c4c2848726be1361f6dee3c33e7551b857
Author: Patrick Rudolph
Date: Tue Nov 12 16:30:14 2019 +0100
cpu/x86/lapic: Support
rite_around and lapic_read_around
functions that pop up. From my perspective, none of this is needed and you can
just use the usual lapic_read and lapic_write functions.
Julian
>
> On Mon, Oct 4, 2021 at 7:14 AM Julian Stecklina
> wrote:
> >
> > Hello,
> >
>
Hello,
I was looking at the Local APIC code in coreboot and was wondering about
`lapic_write_atomic` in src/include/cpu/x86/lapic.h. This uses an atomic XCHG to
write to Local APIC registers. I would like to understand why this would be
necessary, because none of the OSes I've seen or worked on do
in production - so setting this up in a
> virtualized environment shouldnt be a problem at all. To be honest, I
> would not start with the tianocore one, use one of the forks ;)
>
> Best,
>
> On 4/16/21 1:44 PM, Julian Stecklina wrote:
> > On Thu, 2021-04-15 at 16:49 +,
On Thu, 2021-04-15 at 16:49 +, Andy Pont wrote:
> Julian wrote…
>
> > Is anyone actually actively using TianoCore EDK2 on top of coreboot or is
> > support experimental in general?
> We have platforms that are using Matt’s UEFIPayload package to boot
> either Linux or Windows. The mainboards
On Thu, 2021-04-15 at 17:11 +, Peter Stuge wrote:
> How does Nix deal with other cross-toolchains? That's essentially
> what the coreboot toolchain is, so maybe you can find inspiration
> there.
The short story is: It doesn't deal very well with software that tries to build
its own toolchain.
Hi,
I'm trying to build Coreboot with Nix [1] and am facing some issues. I'm
wondering whether someone has already tried this before and can give some
pointers. My specific problem is how to nicely package the toolchain that
coreboot requires.
Any hints are appreciated. :)
I did discover https:/
On Mon, 2021-03-29 at 11:36 -0500, Matt DeVillier wrote:
> Tianocore with the COREBOOTPAYLOAD option is my (heavily modified)
> fork of the now-deprecated CorebootPayloadPkg package which works on
> Intel Core-based platforms Sandybridge and newer. No attempt has been
> make to get it working under
On Mon, 2021-03-29 at 17:45 +0300, Julian Stecklina wrote:
> I'm currently trying to get Tianocore EDK2 running as a Coreboot payload in
> Qemu
> and meeting with limited success, though. I have a working configuration for
> the
> qemu q35 target. Building it for and runni
Hello Coreboot Developers!
First, I want to say that it is really a joy to work with Coreboot. The code is
well-written and of high-quality. :)
I'm currently trying to get Tianocore EDK2 running as a Coreboot payload in Qemu
and meeting with limited success, though. I have a working configuration
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