On Wed, Feb 18, 2015 at 3:14 PM, Carl-Daniel Hailfinger
c-d.hailfinger.devel.2...@gmx.net wrote:
Hi,
I am currently planning to set up a test system with 5 (later up to 10)
machines boot testing each new coreboot commit. This test system will be
serviced (i.e. recovery from bricking) Mo-Fr
My C720 shuts down as well. Someone in this thread suggested that it was
related to whether or not the adapter is connected:
https://productforums.google.com/forum/#!topic/chromebook-central/gjSnZJeMEls%5B1-25-false%5D
I've yet to have it shut down when the adapter is connected, whether or not
I've seen it used for HyperTransport. HT settings survive a warm_reset,
but not a hard_reset. I'm not sure if that's the only case, though.
Thanks,
Myles
On Thu, Jul 4, 2013 at 1:23 PM, Andrew Wu andrewwu...@gmail.com wrote:
Hello,
I am porting coreboot to our own product(Vortex86EX). I
On Thu, Oct 13, 2011 at 1:47 AM, Stefan Reinauer
stefan.reina...@coreboot.org wrote:
* Myles Watson myle...@gmail.com [111012 08:19]:
On Tue, Oct 11, 2011 at 10:13 PM, Oskar Enoksson e...@lysator.liu.se wrote:
I get the following warnings:
APIC: 00 missing read_resources
APIC: 01 missing
On Tue, Oct 11, 2011 at 10:13 PM, Oskar Enoksson e...@lysator.liu.se wrote:
I get the following warnings:
APIC: 00 missing read_resources
APIC: 01 missing read_resources
APIC: 02 missing read_resources
APIC: 03 missing read_resources
I2C: 01:08 missing read_resources
I2C: 04:50 missing
On Thu, Apr 28, 2011 at 4:37 AM, Thom Lauret diracsh...@gmail.com wrote:
I see the nForce Pro 3600 MCP55 is supported in coreboot.
Can anyone tell me if the nForce Pro 3050 IO-55 is also supported ?
If it's the companion chip, then yes. It just shows up in the device
tree as a second MCP55.
On Thu, Mar 31, 2011 at 4:50 AM, Joseph Smith j...@settoplinux.org wrote:
On Tue, 29 Mar 2011 18:20:45 -0400, Brandon ssjgoku...@aol.com wrote:
Hello. I have a Tyan Trinity S1857 board and according to your
compatible chipset list, it's chipset (Intel 440BX) is compatible. Is
there anyway I
sorry to bother you directly, but Peter suggested to send the question
below to you directly, you may have an answer :)
No problem.
while adding support for the Lenovo PMH7 Embedded Controller,
i was wondering about the index parameter for new_resource().
From looking at the coreboot
Try:
sudo lspci -xxx -s 18.0
Then look at the line that starts with e0:
mine is:
e0: 03 00 00 03 03 01 40 40 ...
From the BKDG:
Configuration Base and Limit 0-3 Registers Function 1: Offset E0h, E4h,
E8h, ECh
Remember that the byte order is little endian, and my
On Thu, Jan 27, 2011 at 5:29 AM, Joseph Smith j...@settoplinux.org wrote:
Hello,
Working on a new CK804 board
Which board did you base it on? What are the differences?
and I have it almost booting but it seems the
resource allocator does not like / or want to enumerate the CK804.
It fails
On Thu, Jan 27, 2011 at 6:38 AM, Joseph Smith j...@settoplinux.org wrote:
On Thu, 27 Jan 2011 06:15:34 -0700, Myles Watson myle...@gmail.com wrote:
On Thu, Jan 27, 2011 at 5:29 AM, Joseph Smith j...@settoplinux.org
wrote:
Hello,
Working on a new CK804 board
Which board did you base
Log:
Change fadt revision back to 3.
The AcpiPmaCntBlk have to be set.
Further research is needed to find out why.
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Zheng Bao zheng@amd.com
Modified:
trunk/src/southbridge/amd/sb800/early_setup.c
I'd guess that it's left over from another era, but I'm not sure. Is
there another use for subtractive resources?
Well in general I think port 80 is good example of subtractive resource
decoding.
I agree.
What I meant was... When should we declare subtractive resources in
coreboot? Do
That doesn't happen, because the if (subbus... is in the for loop, which
checks for NULL. the search_bus_resources() is always called outside the
for loop.
You're right. I should have looked at the code first, instead of just
the patch. There wasn't enough context.
If there is no bus
diff --git a/src/devices/device_util.c b/src/devices/device_util.c
index 9081a36..d761cba 100644
--- a/src/devices/device_util.c
+++ b/src/devices/device_util.c
@@ -583,8 +583,9 @@ void search_bus_resources(struct bus *bus, unsigned
long type_mask,
if
On Mon, Jan 10, 2011 at 6:27 AM, Sven Schnelle sv...@stackframe.org wrote:
Myles Watson myle...@gmail.com writes:
diff --git a/src/devices/device_util.c b/src/devices/device_util.c
index 9081a36..d761cba 100644
--- a/src/devices/device_util.c
+++ b/src/devices/device_util.c
@@ -583,8 +583,9
On Sat, Jan 8, 2011 at 5:25 AM, Jouni Mettälä jtmett...@gmail.com wrote:
Here is updated patch with l2_cache.c added.
I think it's missing l2_cache.h now.
Thanks,
Myles
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Martins,
It should be on the list of supported motherboards. Sorry about that. It's
been a while since I was involved in testing it, so you should have a backup
chip ready (as always). It should just work, but if it doesn't, send the
serial output to the list.
Thanks,
Myles
-Original
On Wed, Dec 29, 2010 at 12:21 PM, Roger rogerx@gmail.com wrote:
Which target within make menuconfig is best for this 440BX Intel DFI P2XBL
REV. D Board?
Single Processor Board w/ 1GB RAM (3) slots.
SuperIO: WINBOUND 83977EF-AW
00:00.0 Host bridge: Intel Corporation 440BX/ZX/DX -
On Wed, Dec 29, 2010 at 12:05 PM, Nils njaco...@hetnet.nl wrote:
Move hardcoded IRQ defining from northbridge.c to irq_tables.c .
There's also an added init function for the WYSE board. Did you mean
to add it? It looks like it's only printing.
Thanks,
Myles
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On Wed, Dec 29, 2010 at 12:04 PM, Nils njaco...@hetnet.nl wrote:
Add a MSR printing function to northbridge.c like in the Geode LX code.
It's surprising to have it included
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL = BIOS_ERR
but then have all the print statements be BIOS_DEBUG.
Thanks,
Myles
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Acked-by: Myles Watson myle...@gmail.com
Rev 6221.
Thanks,
Myles
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On Wed, Dec 29, 2010 at 12:05 PM, Nils njaco...@hetnet.nl wrote:
-Clean up some comments.
-Remove some white spaces.
-Remove some leading zeros.
-Fix a typo in LX code.
Signed-off-by: Nils Jacobs njaco...@hetnet.nl
Rev 6219.
Thanks,
Myles
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To begin with I read everything I found on your web page and bought a
spare BIOS
chip (hopefully the correct one :p . I downloaded and built seabios to use
as a
payload and then built a coreboot image for the M4A78EM mobo which I am
ready to
flash as soon as I get my new BIOS chip.
On Fri, Dec 17, 2010 at 1:50 PM, Stefan Reinauer
stefan.reina...@coresystems.de wrote:
Can we automatically determine the value of RAMTOP during build time?
Yes. It's a config variable. It's not the top of physical RAM, it's
the top of what coreboot will use.
Thanks,
Myles
On 17.12.2010, at
On Fri, Dec 17, 2010 at 2:03 PM, Stefan Reinauer ste...@coreboot.org wrote:
* Myles Watson myle...@gmail.com [101217 22:01]:
On Fri, Dec 17, 2010 at 1:50 PM, Stefan Reinauer
stefan.reina...@coresystems.de wrote:
Can we automatically determine the value of RAMTOP during build time?
Yes
On Tue, Dec 7, 2010 at 8:44 AM, Scott Duplichan sc...@notabs.org wrote:
On Thu, Dec 2, 2010 at 9:17 AM, Myles Watson myle...@gmail.com wrote:
Why does the current code for handling fixed resources allow the mmconf
space to get allocated to a PCI device? Function avoid_fixed_resources
calls
I don't see any reason not to move that resource into the northbridge
to avoid that issue. It's a simple fix. Is there a good reason for
having the MMCONF BAR in the APIC cluster?
This is what I was thinking. Build tested only.
Signed-off-by: Myles Watson myle...@gmail.com
Oh
Why does the current code for handling fixed resources allow the mmconf
space to get allocated to a PCI device? Function avoid_fixed_resources
calls function constrain_resources, which recursively searches the
device tree for fixed io and memory resources. The ioapic fixed memory
address is
On Thu, Dec 2, 2010 at 9:17 AM, Myles Watson myle...@gmail.com wrote:
Why does the current code for handling fixed resources allow the mmconf
space to get allocated to a PCI device? Function avoid_fixed_resources
calls function constrain_resources, which recursively searches the
device tree
I don't see any reason not to move that resource into the northbridge
to avoid that issue. It's a simple fix. Is there a good reason for
having the MMCONF BAR in the APIC cluster?
This is what I was thinking. Build tested only.
Signed-off-by: Myles Watson myle...@gmail.com
Thanks
The diff to that in the K8 version is this (in tolm_test()):
- if (!best || (best-base new-base))
+ /* Skip VGA. */
+ if (!best || (best-base new-base new-base 0xa)) {
Small fix which could also be moved into the global tolm_test(). Depending on
whether or not
On Sat, Nov 20, 2010 at 5:30 AM, ali hagigat hagigat...@gmail.com wrote:
Would you please tell me how Coreboot jumps to the label,
protected_start in src/cpu/x86/32bit?
There is a jump instruction (jmp protected_start) in reset16.inc but
it seems it will never be executed.
If you have
@@ -194,6 +194,19 @@
giv++;
}
it8712f_exit_conf();
+
+ printk(BIOS_INFO, it8712f gpio: Setting DDR2 voltage to 1.80V\n);
Maybe this should be BIOS_SPEW. If it's the standard, I don't think
it needs to be seen every boot.
Acked-by: Myles Watson myle...@gmail.com
Modified: trunk/src/lib/malloc.c
==
--- trunk/src/lib/malloc.cWed Nov 10 01:14:32 2010(r6054)
+++ trunk/src/lib/malloc.cWed Nov 10 03:00:32 2010(r6055)
@@ -4,7 +4,7 @@
#if
On Tue, Nov 9, 2010 at 7:53 PM, Stefan Reinauer
stefan.reina...@coresystems.de wrote:
On 09.11.2010, at 18:08, Myles Watson myle...@gmail.com wrote:
Modified: trunk/src/lib/malloc.c
==
--- trunk/src/lib/malloc.c
Is there any fast method to read the onboards NIC mac address
faster?
ip l sh eth0|grep link/ether|awk '{print $2}'
I know that this is possible via commands on the shell, but you can't be
sure
that you select the onboard NIC with that method, because when a second
NIC is
used in that
as quad rank capable
that wasn't marked that way before, but I can't tell if the original
options are set correctly.
In this regard, the tree with this patch is as good as without.
Agreed.
Acked-by: Myles Watson myle...@gmail.com
Thanks,
Myles
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simplified the patch. TINYBOOTBLOCK can come later.
It compiles.
Signed-off-by: Myles Watson myle...@gmail.com
Thanks,
Myles
Index: svn/src/southbridge/via/vt8231/vt8231_enable_rom.c
===
--- /dev/null
+++ svn/src/southbridge/via/vt8231
Is this rom structure reasonable (missing fallback/romstage?):
It's fine. The romstage (boot block) isn't part of CBFS.
Loading stage image.
Check CBFS header at hangs here
Normally a hang here means that the whole ROM isn't mapped, so trying
to read from the top of the ROM hangs, even
I found and tried CONFIG_CONSOLE_VGA_MULTI. I see a couple of problems
with it. First, it seems to apply only to AMD K8 and family 10h processors
(in my case this is OK). A bigger problem is that it seems to control
VGA on an HT link by HT link basis. One problem there is that an HT link
One problem is that the in-box ATI driver for the UMA graphics is
unstable.
Even with the factory BIOS?
So to get Win7 installed, I must add a PCI video card. When Win7 is
installed with the PCI video card present, device manager reports that the
UMA graphics device cannot find enough free
On Thu, Oct 28, 2010 at 11:48 AM, Scott Duplichan sc...@notabs.org wrote:
] One problem is that the in-box ATI driver for the UMA graphics is
] unstable.
]Even with the factory BIOS?
The reference BIOS works fine, so this is a coreboot problem. I have
added missing family 10h code to the
Thanks for the suggestion. What I am really looking for is the
special handling that a commercial BIOS does for legacy video
devices. Say you have a typical desktop UMA board. If you add a
PCI video card, Windows resource manager will not report any
resource conflicts. The same is not true
Last night, I thought I would just learn about gas macros and do it
that way. It was more difficult than I thought. I cannot even find
examples of gas macros that use arguments. A C style macro seemed
possible, but I found when gas processes it the needed ?: does not
work. So I ended up with
Good point. Best would be a 'macro' that allows writing:
movl highestSetBit (busn), %eax
But that is not possible apparently. How about then, back
to inlined code with the extra error checks:
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Myles Watson myle...@gmail.com
On Sun, Oct 17, 2010 at 11:17 PM, Scott Duplichan sc...@notabs.org wrote:
] Hi all,
]
] Scott, thanks on working on that! The resource overlap is bit pitty -
] it belongs to style - Oh I haven't thought of that.
]I think this was heavily discussed a while back, and lead to some
]naughty work
On Mon, Oct 18, 2010 at 6:48 AM, Arne Georg Gleditsch
arne.gledit...@numascale.com wrote:
Rudolf Marek r.ma...@assembler.cz writes:
Please can you help here? Also I tried to have a look how the non-posted
support
could be added but it looks like it must be done somewhat inside the resource
On Mon, Oct 18, 2010 at 12:12 AM, Rudolf Marek r.ma...@assembler.cz wrote:
Hi Myles,
Please can you help here? Also I tried to have a look how the non-posted
support could be added but it looks like it must be done somewhat inside the
resource allocator. Please can you help with that too?
On Sun, Oct 17, 2010 at 11:39:46PM +0200, Uwe Hermann wrote:
- Renamed sblk to sblink (the name of the register bits as per
BIOS + Kernel Developer's Guide for AMD Athlon 64 AMD Opteron
Processors,
chapter 3.3.8.
Hm, I noticed that the K8/Fam10h code uses sblk as
.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Myles Watson myle...@gmail.com
+ #if !defined (CONFIG_CPU_AMD_MODEL_10XXX) !defined
(CONFIG_CPU_AMD_MODEL_14XXX)
mdelay(10);
+ #endif
printk(BIOS_SPEW, Deasserting INIT.\n);
@@ -144,6 +146,9 @@
#endif
On Mon, Oct 18, 2010 at 11:29 AM, Scott Duplichan sc...@notabs.org wrote:
For AMD family 10h processors, msr c0010058 is always programmed
for 256 buses, even if fewer are configured. This patch lets msr
c0010058 programming use the configured bus count, CONFIG_MMCONF_BUS_NUMBER.
Tested with
On Mon, Oct 18, 2010 at 1:11 PM, Arne Georg Gleditsch
arne.gledit...@numascale.com wrote:
Myles Watson myle...@gmail.com writes:
On Mon, Oct 18, 2010 at 6:48 AM, Arne Georg Gleditsch
arne.gledit...@numascale.com wrote:
On a similar note: I'm looking at a southbridge that has its own notion
could
insert the correct size there.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Myles Watson myle...@gmail.com
Index: src/cpu/amd/car/cache_as_ram.inc
===
--- src/cpu/amd/car/cache_as_ram.inc (revision 5965
in those cases. The following patch uses
] a compile time check to identify CPUs where the change is known
] to work.
Signed-off-by: Scott Duplichan sc...@notabs.org
Acked-by: Myles Watson myle...@gmail.com
Thanks,
Myles
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On Mon, Oct 18, 2010 at 8:06 PM, Stefan Reinauer
stefan.reina...@coresystems.de wrote:
On 18.10.2010, at 10:44, Myles Watson myle...@gmail.com wrote:
On Mon, Oct 18, 2010 at 11:29 AM, Scott Duplichan sc...@notabs.org wrote:
+ #elif (CONFIG_MMCONF_BUS_NUMBER == 4)
+ orl $2, %eax
On Sat, Oct 16, 2010 at 3:37 PM, Scott Duplichan sc...@notabs.org wrote:
Hello,
I am testing with mahogany_fam10h and mmconf_base_address at e000.
I find that if I add a pci video card, coreboot assigns e000 to one
of the uma graphics bars. This range is already in use for pcie mmio.
I am not planning to do a lot of little patches and abuild and boot test all
of them separately as that cost me a lot of extra time.
Being part of a community certainly takes more of your time. We hope
that the end product is better because of it. When you spend more
time to make reviewing
On Wed, Oct 13, 2010 at 4:05 PM, fengwei zhang namedy...@gmail.com wrote:
Hi,
I am new to coreboot. Do you guys know where printk() statement go in
coreboot source code?
e.g. printk(BIOS_DEBUG, %s\n, msg);
LXR can be helpful for browsing the code. printk is a macro defined
in console.h
On Wed, Oct 13, 2010 at 2:51 PM, Nils njaco...@hetnet.nl wrote:
***Ping***
It would be nice if someone finds the time to ack/commit or comment my patch.
Your patch is rather long. It would be easier to review if you split
out the white space comment fixes, then the usage of msr names
On Thu, Oct 14, 2010 at 3:02 PM, Nils njaco...@hetnet.nl wrote:
Hello Myles,
Thanks for the review.
Op donderdag 14 oktober 2010 18:53:43 schreef u:
Your patch is rather long. It would be easier to review if you split
out the white space comment fixes, then the usage of msr names
instead
If so, the bios chip might be the SST thing near the white connector
in the
bottom left quadrant of the board. I think it's an LPC style chip.
Having
another chip to flash instead of that one would mean that you could
keep your
oringinal untouched. I think that usually those types of chips
Does that mean that FC_PGA370 is simply PGA370 + CAR, or do PGA370 sockets
really not support SSE2 chips?
Not sure if the socket is the correct place to select either of
MMX/SSE/SSE2 anyway, that's a CPU-property and should probably be
selected in model_* (even if for newer CPUs all of those
If so, the bios chip might be the SST thing near the white connector
in the
bottom left quadrant of the board. I think it's an LPC style chip.
Having
another chip to flash instead of that one would mean that you could
keep your
oringinal untouched. I think that usually those types of chips
On Sun, Oct 10, 2010 at 9:48 PM, Liu Tao liutao1...@gmail.com wrote:
Hello,
the original code reads cpu ht speed from HT chain 0's register.
the patch fix it to read the register from the chain which SB chip is on.
Signed-off-by: Liu Tao liutao1...@gmail.com
Acked-by: Myles Watson myle
into Kconfig.
Signed-off-by: Myles Watson myle...@gmail.com
Acked-by: Uwe Hermann u...@hermann-uwe.de
Thanks,
Myles
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On Thu, Oct 07, 2010 at 03:55:41PM -0600, Myles Watson wrote:
Kconfig_if.diff : use if instead of depends on to avoid typos
socket_type.diff : don't define socket_type and dimm_type when they
aren't used
raminit_sysinfo.diff : get rid of another define
Signed-off-by: Myles Watson myle
On Wed, Oct 6, 2010 at 10:24 AM, STEMMELIN, FREDERIC (FREDERIC)** CTR
** frederic.stemme...@alcatel-lucent.com wrote:
Hello,
i have just tried, and it fails.
Good to know. Thanks.
I created a new folder, downloaded latest coreboot and seabios version (no
patching at all).
Build both
On Tue, Oct 5, 2010 at 4:56 AM, Patrick Georgi patr...@georgi-clan.de wrote:
Hi,
attached patch does:
- move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1
- move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug
port enabled southbridges
- drop USB debug
On Tue, Oct 5, 2010 at 11:16 AM, Patrick Georgi patr...@georgi-clan.de wrote:
Am 05.10.2010 17:32, schrieb Myles Watson:
On Tue, Oct 5, 2010 at 8:41 AM, Patrick Georgi patr...@georgi-clan.de
wrote:
Hi,
attached patch moves a couple more config flags out of romstage:
CK804_USE_NIC
Subject: [coreboot] [patch] avoid printf format warning in debugging path
Use %p instead of %x to print void *.
I didn't see the patch for this one or the previous one.
Thanks,
Myles
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On Tue, Oct 5, 2010 at 1:36 PM, Jonathan A. Kollasch
jakll...@kollasch.net wrote:
Remove duplicate line from pci_ids.h.
Signed-off-by: Jonathan Kollasch jakll...@kollasch.net
Acked-off-by: Jonathan Kollasch jakll...@kollasch.net
Rev 5916.
Thanks,
Myles
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On Tue, Oct 5, 2010 at 1:34 PM, Jonathan A. Kollasch
jakll...@kollasch.net wrote:
Use %p instead of %x to print void *.
Signed-off-by: Jonathan Kollasch jakll...@kollasch.net
Acked-by: Jonathan Kollasch jakll...@kollasch.net
Rev 5915.
Thanks,
Myles
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On Sun, Oct 3, 2010 at 5:10 PM, Peter Stuge pe...@stuge.se wrote:
Rudolf just found a bug in the sb700 code:
u32 dword;
..
dword = pci_read_config8(dev, 0x64);
dword |= 1 10;
pci_write_config8(dev, 0x64, dword);
And I'm ranting now, because a pci_set8() macro/function could have
found
On Mon, Oct 04, 2010 at 01:19:07AM +0200, Peter Stuge wrote:
Stefan Reinauer wrote:
+config CPU_ADDR_BITS_MASK
Such stuff belongs into an include file, not into Kconfig.
Good point! I agree completely if it works in practise.
Are you guys suggesting something like this?
On Fri, Oct 1, 2010 at 1:15 AM, Warren Turkal w...@penguintechs.org wrote:
Notice that it is also changing the base of the CAR area and,
That one scares me. IIRC that's a sensitive value. Or am I wrong?
I think it should be fine as long as the size of the CAR area is changed at
the same
repository service wrote:
lzma.c is already included unconditionally in the same file.
..
-ramstage-$(CONFIG_COMPRESSED_PAYLOAD_LZMA) += lzma.c
Why include lzma.c unconditionally if the payload will not be
compressed?
CONFIG_COMPRESSED_PAYLOAD_LZMA !=
Modified:
trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
trunk/src/cpu/intel/model_6fx/cache_as_ram.inc
It looks like src/cpu/intel/car/cache_as_ram.inc could use the same love.
I'd be interested to see how much uglier it made these
I'd like to redirect the output of iasl to a file. Patch attached.
Here's a little justification:
http://qa.coreboot.org/log_buildbrd.php?revision=5900device=serengeti_cheetahvendor=amdnum=2
Signed-off-by: Myles Watson myle...@gmail.com
Thanks,
Myles
Index: Makefile
Myles Watson wrote:
lzma.c is already included unconditionally in the same file.
Why include lzma.c unconditionally if the payload will not be
compressed?
..
If build coreboot with no payload (CONFIG_COMPRESSED_PAYLOAD_LZMA = n),
then add a payload with cbfstool, how does
On Fri, Oct 01, 2010 at 11:55:49AM -0600, Myles Watson wrote:
Modified:
trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
trunk/src/cpu/intel/model_6fx/cache_as_ram.inc
It looks like src/cpu/intel/car/cache_as_ram.inc could use
This was surprising:
+ * Copyright (C) 2000,2007 Ronald G. Minnich rminn...@gmail.com
+ * Copyright (C) 2007-2008 coresystems GmbH
The macros are well named. I'd prefer including comments only for ones that
need an explanation.
+/* Disable cache. */
+#define disable_cache() \
+ movl
On Fri, Oct 1, 2010 at 3:35 PM, Uwe Hermann u...@hermann-uwe.de wrote:
On Fri, Oct 01, 2010 at 12:01:59PM -0600, Myles Watson wrote:
I'd like to redirect the output of iasl to a file. Patch attached.
Here's a little justification:
http://qa.coreboot.org/log_buildbrd.php?revision=5900device
On Fri, Oct 01, 2010 at 03:46:31PM -0600, Myles Watson wrote:
This was surprising:
+ * Copyright (C) 2000,2007 Ronald G. Minnich rminn...@gmail.com
+ * Copyright (C) 2007-2008 coresystems GmbH
Yeah, I copied most of the stuff from model_6ex or something like that,
hence the (C
IMHO the patch makes it really hard to actually see what the code does.
I think Idwer was recently running into a problem where the use of
post_code would trash %eax were hard to comprehend. Now we seem have a
lot more code that comes from somewhere else and touches registers
without it being
For the record, I checked a representative set of the boards to make
sure they generate the same .config before and after this change.
Since it's relatively easy to check, I think it's worthwhile to make sure
that no .config settings are changed when cleaning up settings.
1.
I'm surprised that the #defines were commented out.
Acked-by: Myles Watson myle...@gmail.com
Thanks,
Myles
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I am looking for some comments on the following patch. It unifies the
socket 940 cache-as-ram implementation. Previously, the affected boards
had their own CAR options in their Kconfig files. There is a default set
of CAR configs in the socket.
Does anyone have comments on why this patch
On Thu, Sep 30, 2010 at 4:19 PM, Patrick Georgi patr...@georgi-clan.de wrote:
Hi,
attached patch moves several config flags that, for historical reasons,
were put in romstage.c into Kconfig.
+choice
+ prompt Chipset variant
+ default I945GM
+ depends on
On Thu, Sep 30, 2010 at 4:31 PM, Patrick Georgi patr...@georgi-clan.de wrote:
Am 01.10.2010 00:24, schrieb Myles Watson:
+choice
+ prompt Chipset variant
+ default I945GM
+ depends on NORTHBRIDGE_INTEL_I945
+ help
+ Different i945 variants require slightly different
On Wed, Sep 29, 2010 at 2:54 AM, Arne Georg Gleditsch
arne.gledit...@numascale.com wrote:
Hi,
I'm trying (again) to get my head around how the different pieces of
HT-enumeration interacts... Do we have any documentation on the
variables
HT_CHAIN_UNITID_BASE
HT_CHAIN_END_UNITID_BASE
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org]
On Behalf Of Uwe Hermann
Subject: [coreboot] [PATCH] Factor out fill_processor_name() and
strcpy()functions.
Thanks for factoring it out. Why not put it in src/cpu/x86? Does it need
its own directory?
Maybe there
-Original Message-
From: Uwe Hermann [mailto:u...@hermann-uwe.de]
Sent: Tuesday, September 28, 2010 3:18 PM
To: Myles Watson
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] [PATCH] Factor out fill_processor_name() and
strcpy()functions.
On Tue, Sep 28, 2010 at 02:28:12PM
Acked-by: Myles Watson myle...@gmail.com
Thanks,
Myles
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Thanks for fixing it!
Acked-by: Myles Watson myle...@gmail.com
I think it would be nice to keep the mc146818rtc.h include close to
the option table include where possible. I did it for a few boards to
see what you thought. It also removes a stray space.
Signed-off-by: Myles Watson myle
Modified: trunk/src/mainboard/hp/dl165_g6_fam10/Kconfig
==
--- trunk/src/mainboard/hp/dl165_g6_fam10/Kconfig Fri Sep 24 19:35:32
2010 (r5831)
+++ trunk/src/mainboard/hp/dl165_g6_fam10/Kconfig Fri
I also found that we might be able to use __DATE__ and __TIME__
(preprocessor macros) instead of calling date(1). Any opinion on that?
I have a mild preference for macros over system calls.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Myles Watson myle...@gmail.com
Now after remowing my Intel PRO1000MT server network card from
PCI-X slot 6, i can boot without any problems :)
..the PCI-X should also work. I think it may be good to investigate
why it gets such a high bus number.
The K8 code assigns bus numbers that way. The primary southbridge
link gets
On Sun, Sep 19, 2010 at 8:16 AM, STEMMELIN, FREDERIC (FREDERIC)** CTR
** frederic.stemme...@alcatel-lucent.com wrote:
Now here are my results with the patched Memtest86+ version 4.1.
Check the attached files.
As you can see it is far way better, even if it is not working, at least i
can see
GRUB_CMDLIN_LINUX_DEFAULT=verbose in /etc/default/grub and sudo
update- grub
I will do it, with original VGA bios and prebuild seabios too.
Since there's no built-in video card on the s2895, there shouldn't be a VGA
BIOS for the board. I was thinking of the s2892.
My s2895 boots fine, so
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