I'm seeing breakage when building traverse/geos. Is this a known issue?
[philipp@builder ~/coreboot]$ make V=1
...
CC romstage.inc
gcc -m32 -Wa,--divide -fno-stack-protector -Wl,--build-id=none -MMD -Isrc
-Isrc/include -Ibuild -Isrc/arch/x86/include -Isrc/devices/oprom/include
-incl
I'm writing a Linux platform driver for a couple of Geode based boards, and was
thinking that it would be nice if there was a canonical/prototypical stub
routine that came with coreboot that detected the signature on a target system.
That is, I could paste this code into a platform driver (for i
On 7/30/11 7:07 PM, Philip Prindeville wrote:
> I'm seeing breakage when building traverse/geos. Is this a known issue?
>
> [philipp@builder ~/coreboot]$ make V=1
> ...
> CC romstage.inc
> gcc -m32 -Wa,--divide -fno-stack-protector -Wl,--build-id=none -MMD
Anyone?
On 7/31/11 11:41 AM, Philip Prindeville wrote:
> I'm writing a Linux platform driver for a couple of Geode based boards, and
> was thinking that it would be nice if there was a canonical/prototypical stub
> routine that came with coreboot that detected the signatu
I'm adding a Geos platform driver that needs to be able to confirm that it's
running on the correct hardware, and it does this by locating the Coreboot
tables and parsing them for the vendor/part fields.
Unfortunately, it's not working entirely.
I borrowed code from flashrom's cbtable.c and twe
I see the following when I boot up below, and when I go looking for the
coreboot tables I find it at 0x500... with the first entry at 0x518 being a
FORWARD record pointing to 0x1f7d1400.
However, when I try to access that pointer, the system panics.
How do I get at the RAM in this region here?
On 8/12/11 12:49 AM, Rudolf Marek wrote:
>> How do I get at the RAM in this region here?
>
> ioremap
>
> Rudolf
>
Ok, thanks. One other question: the pointer that's being left in memory for the
forward record... is that a 32-bit linear address? Or is it a funky
segment:offset style address f
Locate and parse coreboot tables, if present.
Tested/verified with Traverse Technologies GEOS SBC. Used in platform driver to
detect running on
correct platform.
Anyone have an issue with me upstreaming this to linux-next?
Signed-off-by: Philip Prindeville
---
--- a/lib/Kconfig 2011-08
1/1] libpayload: add support for finding and
parsing Coreboot BIOS tables
Date: Fri, 19 Aug 2011 16:23:27 -0700
From: Andrew Morton
To: Philip Prindeville
On Thu, 18 Aug 2011 20:55:56 -0700
Philip Prindeville wrote:
> Hi Andrew,
>
> Any chance this could make it in for 3.2?
Perhaps. B
On 8/22/11 3:01 PM, Andrew Morton wrote:
> On Sun, 21 Aug 2011 17:01:28 -0700
> Philip Prindeville wrote:
>
>> Attached.
>
> oookay. I'll await a formal patch with all the cc's, etc.
>
> As for the "upstream" version: if/when this patch is merged
On 8/22/11 4:00 PM, Andres Salomon wrote:
> On Mon, 22 Aug 2011 15:01:51 -0700
> Andrew Morton wrote:
>
>> On Sun, 21 Aug 2011 17:01:28 -0700
>> Philip Prindeville wrote:
>>
>>> Attached.
>>
>> oookay. I'll await a formal patch with all th
On 12/23/11 9:16 PM, ron minnich wrote:
> I'm just getting back to coreboot. Is libpayload used verbatim in the
> kernel? The phys/virt map in coreboot is 1:1 by design. The mapping
> seems unnecessary to me. Just wondering.
>
> ron
>
The code is being borrowed to use in linux as well to help pa
Ok, I build coreboot's trunk and selected the target Alix2D, but managed to
brick the device:
coreboot-4.0-1933-gded9388-dirty Wed Dec 28 16:14:58 MST 2011 starting...
MSR GLCP_SYS_RSTPLL (4c14) value is 059c:182e
Configuring PLL.
coreboot-4.0-1933-gded9388-dirty Wed Dec 28 16:14:58
On 12/29/11 4:30 AM, Benjamin Henrion wrote:
> On Thu, Dec 29, 2011 at 3:22 AM, Philip Prindeville
> wrote:
>> Ok, I build coreboot's trunk and selected the target Alix2D, but managed to
>> brick the device:
>>
>> coreboot-4.0-1933-gded9388-dirty Wed Dec 28 1
I was looking at the devicetree.cb values for the alix2 versus what I see on my
alix6:
root@OpenWrt:/# rdmsr 0x51400025
1002
root@OpenWrt:/# rdmsr 0x5140004e
effd00c0
root@OpenWrt:/#
I'm not sure how significant these differences are:
chip northbridge/amd/lx
device pci_domain 0 on
When I boot coreboot (the alix2 image) on a 6F2 I get the following spew.
==
Changing serial settings was 13/5 now 3/0
In resume (status=0)
In 32bit resume
Attempting a hard reboot
WARNING - Timeout at i8042_wait_write:51!
coreboot-4.0-1936-g33dd7a8-dirty Wed Jan 4 12:20:50 MST 2012 st
Ok, didn't know that was still in my "git commit" list waiting for a "git
push"...
Should have checked.
On 1/6/12 11:53 AM, Philip Prindeville (pprindevi...@gmail.com) wrote:
> Philip Prindeville (pprindevi...@gmail.com) just uploaded a new patch set to
> ger
On 1/6/12 1:31 PM, Patrick Georgi wrote:
> Am 06.01.2012 19:43, schrieb Nils:
>> Correct me if i'm wrong but Geode GX2/LX doesn't have MTRRs.
>> Cache is setup via MSR registers.
> MTRR is usually configured via MSR (0x200 to 0x210, specifically). Not
> sure if Geode does it the same way, but MSR
s it the same way, but MSR doesn't mean "no MTRR".
> See attachment for part of page 494 of the GX2 databook.:)
>
> Philip Prindeville wrote:
>> Caching is bits 30:29 of CR0.
> There are actually a lot more MSR registers for defining cache regions.
&g
Hi.
I'm seeing the following... When rebooting from Linux, Linux shuts down and I see
"machine restart." then the grub prompt, grub eventually tries to load
something, but seems to fail, and I see the Coreboot messages, then I see the grub prompt
again, and the second time it tries to load Lin
On 3/27/11 3:43 PM, Nathan Williams wrote:
On Sat, 2011-03-26 at 22:09 -0700, Philip Prindeville wrote:
Hi.
I'm seeing the following... When rebooting from Linux, Linux shuts down and I see
"machine restart." then the grub prompt, grub eventually tries to load
something, bu
On 3/27/11 4:32 PM, Nathan Williams wrote:
On Sun, 2011-03-27 at 16:09 -0700, Philip Prindeville wrote:
Is there a link to an image for the board (and flashing directions) on your
website?
No, there isn't. Which SST chip do you have? 49LF080A or 49LF004B?
I can send you an image off
On 3/27/11 4:42 PM, Philip Prindeville wrote:
On 3/27/11 4:32 PM, Nathan Williams wrote:
On Sun, 2011-03-27 at 16:09 -0700, Philip Prindeville wrote:
Is there a link to an image for the board (and flashing directions) on your
website?
No, there isn't. Which SST chip do you have? 49L
On 3/28/11 1:37 PM, Carl-Daniel Hailfinger wrote:
> Hi,
>
> [followup to flash...@flashrom.org please]
>
> Am 28.03.2011 01:32 schrieb Nathan Williams:
>> Flashrom is available as a package in OpenWRT, but from memory I think
>> it looks for /dev/cpu/0/msr and OpenWRT has /dev/msr0 instead. Create
Yeah, preferably in USASCII, Latin1, or UTF8.
GB2312 causes all sorts of false positives for my Spam filters.
On Mar 12, 2014, at 6:56 PM, Kurt QH1 Qiao wrote:
> What about mail server run a script that convert HTML mail to be plain text
> mail?
>
> Kurt
> 发件人: coreboot-boun...@coreboot.org
You can do this with Mimedefang (hence the name) in the function
remove_redundant_html_parts().
Mimedefang is callable from both Postfix and Sendmail, since they both use the
libmilter.
In this case, though, coreboot is hosted on Google so we wouldn’t have that
degree of control.
On Mar 13,
On Mar 7, 2014, at 1:42 AM, Paul Menzel
wrote:
>
> Besides that HTML formatting for text only adds advantage in rare cases,
> it also increases message size, which is bad in my case, as I only have
> a 30 MB flat rate on my mobile plan for example.
>
> So could you please recheck your email cl
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