/init/tinybootblock_normal.c
src/arch/i386/init/tinybootblock_simple.c
and bootblock.c itself be removed (the patch does that, but your
patch(1) might not delete the file properly).
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Stefan Reinauer ste
myle...@gmail.com
I updated the patch, with all the boards converted that appeared in
Kconfig after this patch was made, too. There's not a single driver in
src/mainboard left.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
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On 2/23/10 11:13 PM, Riot wrote:
Hi!
I've got a VIA ME6000-LVDS (Board only says: EPIA-M rev B)
Where i can't really confirm the north- and southbridge, as
they're glued to a large passive cooler.
Is that board compatible?
It looks very similar to the via epia-m in the tree. But we
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms
On 2/22/10 1:56 PM, Joseph Smith wrote:
I use die in raminit for memory compatibility checks. If the memory is not
compatible, there is no use moving on...so we die().
I agree... to some extent...
The file I posted does not change the explicit die() calls though but
only the implicit die()
On 2/22/10 1:25 PM, Peter Stuge wrote:
repository service wrote:
+++ trunk/src/cpu/x86/smm/smihandler.c Mon Feb 22 10:32:33 2010
(r5141)
..
@@ -145,8 +146,12 @@
/* Call chipset specific SMI handlers. This would be the place to
* add a CPU or
On 2/22/10 1:33 PM, Peter Stuge wrote:
Stefan Reinauer wrote:
Also, do we want to die() on an assert?
Ideally I would like coreboot to be so structured that an assert just
leads to the current task being aborted, and then we try to
continue as best as possible.
Yes. I agree
On 2/22/10 3:57 PM, Uwe Hermann wrote:
So folks, if you agree that we should clean up coreboot and make it
easier for people, send me an Acked-by: for the above idea.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Uwe Hermann u...@hermann-uwe.de
Awesome, thanks
On 2/22/10 4:45 PM, Uwe Hermann wrote:
--- src/southbridge/intel/i82801gx/i82801gx_pcie.c (revision 5133)
+++ src/southbridge/intel/i82801gx/i82801gx_pcie.c (working copy)
@@ -75,7 +75,7 @@
reg16 |= (1 6);
pci_write_config16(dev, 0x50, reg16);
-#if EVEN_MORE_DEBUG
+#ifdef
On 2/22/10 5:29 PM, ron minnich wrote:
I'm glad this works, but I am afraid I have a concern about it.
I've become opposed to inline assembly on several principles in the
last few years:
I have another one:
- no assembly outside of cpu/ and arch/i386
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On 2/22/10 5:59 PM, Peter Stuge wrote:
ron minnich wrote:
I still try to fancy what that panic room is. Is it the gdb
handler for the case that gdb is enabled?
in my ideal world, the panic room is SerialICE.
That's a nice idea.
I think interesting suggestions for panic
See patch
wow this code could use an indent,... but I just exchanged all the ctrl-d0
by PCI_DEV(0, 0, 0) which took off a significant amount of register pressure
while compiling with romcc.
Enough to keep the code working with the unified assert.h I posted today.
Signed-off-by: Stefan Reinauer
On 2/23/10 12:45 AM, ron minnich wrote:
There's a way to test this?
Not for me... it's 2 boards out of 20+
But we did the same conversion for i945 and i830 before, so it's
generally a good idea.
The smarter thing would be to convert the board to CAR, but if I had to
choose between those
...@assembler.cz
Sorry for leaving this broken for so long... can't fix it, I don't have
the hardware and it's not sold anymore
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don't know if you have an
ICH0 or ICH4, you can't do a coreboot port, because you will fail in so
many other places before and after that.
So folks, if you agree that we should clean up coreboot and make it
easier for people, send me an Acked-by: for the above idea.
Signed-off-by: Stefan
See patch
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On 2/19/10 8:53 PM, Myles Watson wrote:
On Fri, Feb 19, 2010 at 12:46 PM, Stefan Reinauer
ste...@coresystems.de mailto:ste...@coresystems.de wrote:
On 2/19/10 8:42 PM, Myles Watson wrote:
Oh shoot. This broke all the patches I am just preparing... Oh
well.. It'll have to wait
On 2/17/10 7:39 PM, Jeremy Jackson wrote:
On Sat, 2010-01-23 at 09:43 -0700, Myles Watson wrote:
On Sat, Jan 23, 2010 at 8:50 AM, Stefan Reinauer
ste...@coresystems.de wrote:
Hi,
the attached patch does the following:
In Message-ID: 4b5cb231.7030
On 2/16/10 5:11 AM, Timothy Pearson wrote:
Here is a cleaned up and tested version of the SMP APIC autodetect patch.
Signed-off-by: Timothy Pearson tpear...@raptorengineeringinc.com
---
It would of course be helpful to attach the patch. My Webmail client
keeps eating it...
Timothy
On 2/16/10 8:42 PM, Myles Watson wrote:
On Tue, Feb 16, 2010 at 12:02 PM, Stefan Reinauer
ste...@coresystems.de mailto:ste...@coresystems.de wrote:
On 2/16/10 5:11 AM, Timothy Pearson wrote:
Here is a cleaned up and tested version of the SMP APIC
autodetect patch
clean your output directory and start fresh.
Stefan
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without this patch coreboot's romstage will come up with
coreboot-4.0 date. starting..
The patch removes the
Not sure what causes this, but I think romcc assumes that is a
protected instead of an empty string
(Better fix might be to fix that)
Acked-by: Stefan Reinauer ste...@coresystems.de
the right thing to do
Acked-by: Stefan Reinauer ste...@coresystems.de
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dependency list in README.
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See patch
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separate
On 2/10/10 4:29 PM, Stefan Reinauer wrote:
See patch
Some part was missing. New version.
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, as
the directory gets a new timestamp once a file in it is touched. We
don't need to rebuild cbfstool all the time.
Am 10.02.2010 13:25, schrieb Patrick Georgi:
Still
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
On 2/10/10 7:45 PM, Patrick Georgi wrote:
Hi,
Remove uses of the shell to remove double quotes, or to figure out the
current directory (stored in $(PWD) as well)
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
and time
again.
Also more portable xcompile, as dd(1) is dropped (mingw support)
Again,
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Patrick
Acked-by: Stefan Reinauer ste...@coresystems.de
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See patch
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On 2/9/10 9:06 AM, Peter Stuge wrote:
What happens in the build:
kconfig generates config.h, which carries all the CONFIG_* definitions.
The build.h file is created by make rules and contains a couple more
definitions, mostly those with COREBOOT_*, and an include of config.h.
Aha. Could
-by: Stefan Reinauer ste...@coresystems.de
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to a framework.
Acked-by: Stefan Reinauer ste...@coresystems.de
For the future it would be nice if files like
usb.asl/sata.asl/ide.asl/globutil.asl of the AMD RS690/SB600 based
boards could live in southbridge/amd/sb600/acpi
Maybe someone can step up and fix this?
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On 2/1/10 6:58 PM, Uwe Hermann wrote:
On Sun, Jan 31, 2010 at 06:05:38PM +0100, Patrick Georgi wrote:
Am 30.01.2010 15:38, schrieb Stefan Reinauer:
See patch :-)
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
r5096
Maybe not call it 4.0alpha1 but only 4.0
On 2/7/10 5:29 PM, Patrick Georgi wrote:
Then, there are design questions: this libm is made for userland, with a
kernel expected to provide support if anything goes wrong. How does the
math library cope with FPU exceptions? Does it at all?
I have to second that
There are also concerns of
On 2/5/10 5:28 AM, Myles Watson wrote:
-CONFIG_LOGICAL_CPUS = 0x0 - Why would newconfig specify 0 cpus???
LOGICAL_CPUS is code for multiple cores. In this case I'm assuming that
your CPU is single-core.
Also, despite what the name implies, this is a boolean type of value,
0 meaning no
On 2/5/10 5:17 PM, ron minnich wrote:
On Fri, Feb 5, 2010 at 1:29 AM, Stefan Reinauer ste...@coresystems.de wrote:
On 2/5/10 5:28 AM, Myles Watson wrote:
-CONFIG_LOGICAL_CPUS = 0x0 - Why would newconfig specify 0 cpus???
LOGICAL_CPUS is code for multiple cores
to do what FILO does, FILO should be fixed
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not.
What was the problem without the patch?
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On 2/4/10 4:44 PM, Krzysztof Walkiewicz wrote:
Hello everybody,
I have a question: is there any safe method to check if coreboot will
work with my old Toshiba A60-302 laptop?
Yes, there is a very safe method: Check the list of supported systems on
our web page:
See patch.
fixup patch from ticket #152 for coreboot trunk
(http://tracker.coreboot.org/trac/coreboot/ticket/152)
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: src/southbridge/amd/cs5536/cs5536_early_setup.c
On 2/3/10 6:50 PM, Ward Vandewege wrote:
This fixes breakage introduced in r5051.
Thanks,
Ward.
Sorry for the inconvenience.
Acked-by: Stefan Reinauer ste...@coresystems.de
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On 2/2/10 4:25 AM, Bao, Zheng wrote:
Index: src/arch/i386/smp/ioapic.c
===
--- src/arch/i386/smp/ioapic.c(revision 5073)
+++ src/arch/i386/smp/ioapic.c(working copy)
@@ -110,7 +110,7 @@
#endif
/*
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(shows 512MB double sided SO-DIMM in
socket 1 and 64MB single sided onboard memory) and attached patch.
Signed-off-by: Joseph Smith j...@settoplinux.org
Nice!
Acked-by: Stefan Reinauer ste...@coresystems.de
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Dear Silvain,
On 1/31/10 1:34 PM, Sylvain Ageneau wrote:
Hello,
I'd like to announce that tinyscheme
http://tinyscheme.sourceforge.net/home.html can now run as a
coreboot payload.
TinyScheme is a lightweight Scheme interpreter that implements as
large a subset of R5RS as was possible
See patch :-)
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On 1/29/10 9:16 PM, Myles Watson wrote:
* don't turn on WARNINGS_AS_ERRORS for Qemu per default
I disagree with this change. I think it should be noticed when
changes add warnings to a target that is free of them. I think the
goal should be to be able to turn this on for all targets.
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Vendor BIOS, too?
Stefan
with vendor BIOS. Now with the patched version it halts with coreboot
without error messages (the output you see below is what I see until I
press reset button) and with vendor BIOS its reboots at the same point
(after 2 sec).
bye and thx,
Knut Kujat.
Stefan Reinauer
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MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x1511
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
I think we should stay consistent here.
Otherwise:
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difference in UDELAY configuration to newconfig is via/epia
(TSC instead of IO), but given that C3 is shown to support TSC on other
boards, I preferred more regular configurations.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
On 1/24/10 10:27 AM, v...@ru.ru wrote:
How about debuging/loading/using coreboot from a PCI device?
Do you have a pointer to appropriate PCI cards? I guess
Robson/TurboMemory cards won't work, will they?
Stefan
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diff -urN memtest86+-4.00.orig/Makefile memtest86+-4.00/Makefile
--- memtest86+-4.00.orig/Makefile 2009-09-22 02:35:46.0 +0200
+++ memtest86+-4.00/Makefile
On 1/23/10 4:17 PM, Peter Stuge wrote:
Stefan Reinauer wrote:
+++ memtest86+-4.00/linuxbios.c 2010-01-23 12:45:06.0 +0100
..
@@ -54,16 +54,16 @@
}
#define for_each_lbrec(head, rec) \
-for(rec = (struct lb_record *)(((char *)head) + sizeof(*head
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diff -ur memtest86-3.5.orig/Makefile memtest86-3.5/Makefile
--- memtest86-3.5.orig/Makefile 2009-01-06 07:03:23.0 +0100
+++ memtest86-3.5/Makefile 2010-01-23 16:13:09.0 +0100
@@ -8,13 +8,15
.
This adds an additional requirement to superiotool: libpci. I have made
the PCI code conditional on PCI_SUPPORT for now.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Ping?
I guess nobody has that hardware anymore, but anyways
Acked-by: Stefan Reinauer ste
.
Stefan
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See patch
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dev
See patch
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Kontron
/
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drop COREBOOT_V2 and COREBOOT_V4 define. We're not sharing code with v3 anymore
so this ugly hack is no longer needed.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: src/Kconfig
On 1/16/10 8:23 PM, ron minnich wrote:
I'm good with acking the entire series
Acked-by: Ronald G. Minnich rminn...@gmail.com
Thank you!
Committed as revisions r5025-5031.
Stefan
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On 1/17/10 1:40 AM, Carl-Daniel Hailfinger wrote:
Hi Stefan,
Absolutely awesome! Congratulations! This is really great news.
On 16.01.2010 20:09, Stefan Reinauer wrote:
I am especially glad to announce that coresystems GmbH is
releasing coreboot® for the Roda RK886EX a.k.a Rocky III
On 1/16/10 9:12 PM, Peter Stuge wrote:
Stefan Reinauer wrote:
+++ src/mainboard/roda/rk886ex/Kconfig (revision 0)
@@ -0,0 +1,62 @@
+config BOARD_RODA_RK886EX
+bool RK886EX
+select ARCH_X86
+select CPU_INTEL_CORE
+select CPU_INTEL_SOCKET_MFCPGA478
+select
value. Any
other character can still be used as separator however, so the following
syntax still works as expected:
msrtool -i 4c0f=f2f100ff:56960004
Signed-off-by: Peter Stuge pe...@stuge.se
Acked-by: Stefan Reinauer ste...@coresystems.de
Previously, msrtool would assume that MSR
On 1/17/10 4:45 PM, Joseph Smith wrote:
On 01/17/2010 08:47 AM, s...@coreboot.org wrote:
Author: stepan
Date: 2010-01-17 14:47:35 +0100 (Sun, 17 Jan 2010)
New Revision: 5025
Modified:
trunk/src/northbridge/intel/i945/early_init.c
trunk/src/northbridge/intel/i945/raminit.c
Log:
Dear Cristi,
Is this SuperIO chip very different from the generic SMSC ones whose
support code can be found in src/superio/smscsuperio? For avoiding code
duplication it would be nice to move it there if it's not too hard.
Unfortunately, the generic SMSC driver is not suitable, as it assumes
Did they use the Flash or Mask ROM version of the M3885X in the laptop?
M38857M8-XXXHP 32K 1K Mask ROM 8MHz/3.0 to 3.6V
M38858MC-XXXHP 48K 1.5K Mask ROM 8MHz/3.0 to 3.6V
M38859FFHP 60K 2K Flash memory 8MHz/3.0 to 3.6V
in the eye if we
call that a hardware design issue
Stefan
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See patch
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coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: i...@coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
ectool
See patch
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coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: i...@coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
Update
: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
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coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: i...@coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
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coreboot
Sicherheit in der Informationstechnologie (Federal
Office for Information Security, BSI)
A big thank you also goes to everyone who worked with coresystems on
this project.
Best regards,
Stefan Reinauer
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coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax
See patch
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: i...@coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
Support
See patch
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coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: i...@coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
ICH7
See patch
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coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: i...@coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
Add
See patch
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coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: i...@coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
Add
See patch
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: i...@coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
Add
See patch
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: i...@coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
Initial
On 1/15/10 12:57 AM, Peter Stuge wrote:
Unfortunately, msrtool is not
currently available as payload, but perhaps coreinfo can be used to
display MSRs?
(It would be nice to have msrtool diff mode available in coreinfo,
using a file stored in cbfs for comparison!)
I think a diff mode
On 1/15/10 8:20 PM, Peter Stuge wrote:
s...@coreboot.org wrote:
Support for the AMD Geode GX2 Processors to Msrtool.
It seems to work as it was tested
Please do not accept it seems to work for new register
descriptions, always review them against the available
documentation.
On 1/14/10 8:08 PM, ron minnich wrote:
Acked-by: Ronald G. Minnich rminn...@gmail.com
I'd like to suggest solving this in a different way if possible.
Roughly two objections:
Moving coreboot down to 0x4000 is not safe, and we should attempt to fix
it living above 1MB. There are two
On 1/14/10 8:45 PM, Piotr Piwko wrote:
There is a similar function ram_check() in lib/ramtest.c.
Yes, but I don't know how I can force a compilation of /lib/ramtest.c
file during building process.
It already is included in cache_as_ram_auto.c
Just add a line
ram_check(0x,
On 1/14/10 11:33 PM, ron minnich wrote:
On Thu, Jan 14, 2010 at 11:44 AM, Stefan Reinauer ste...@coresystems.de
wrote:
On 1/14/10 8:08 PM, ron minnich wrote:
Acked-by: Ronald G. Minnich rminn...@gmail.com
I'd like to suggest solving this in a different way if possible.
Roughly two
-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Stefan
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