Re: [coreboot] [PATCH] separate build.h and config.h

On 2/10/10 4:29 PM, Stefan Reinauer wrote: > See patch > > Some part was missing. New version. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Am

[coreboot] [PATCH] separate build.h and config.h

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 separate

Re: [coreboot] [PATCH]Remove perl dependency

emove perl > from our dependency list in README. > > > Signed-off-by: Patrick Georgi > Acked-by: Stefan Reinauer -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresyst

[coreboot] [PATCH] Option List Generator

ript with the new one. Signed-off-by: Stefan Reinauer -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführ

Re: [coreboot] build.h dependency

On 2/9/10 9:06 AM, Peter Stuge wrote: >> What happens in the build: >> kconfig generates config.h, which carries all the CONFIG_* definitions. >> The build.h file is created by make rules and contains a couple more >> definitions, mostly those with COREBOOT_*, and an include of config.h. >> >

Re: [coreboot] It's not just v2 anymore

On 2/1/10 6:58 PM, Uwe Hermann wrote: > On Sun, Jan 31, 2010 at 06:05:38PM +0100, Patrick Georgi wrote: > >> Am 30.01.2010 15:38, schrieb Stefan Reinauer: >> >>> See patch :-) >>> >> Acked-by: Patrick Georgi >> > r5096

Re: [coreboot] [PATCH]Clean up ACPI

gt; All boards built with abuilt. > Signed-off-by: Patrick Georgi > Great! ACPI in coreboot is really developing from a mess to a framework. Acked-by: Stefan Reinauer For the future it would be nice if files like usb.asl/sata.asl/ide.asl/globutil.asl of the AMD RS690/SB600 based boards

Re: [coreboot] [PATCH] Math support for libpayload

On 2/7/10 5:29 PM, Patrick Georgi wrote: > Then, there are design questions: this libm is made for userland, with a > kernel expected to provide support if anything goes wrong. How does the > math library cope with FPU exceptions? Does it at all? > I have to second that > There are also concerns

Re: [coreboot] newconfig to Kconfig for Dummies

13 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] libpayload TSC dependency

LO uses this for its timeouts in various places. If there is a better way to do what FILO does, FILO should be fixed -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Register

Re: [coreboot] newconfig to Kconfig for Dummies

On 2/5/10 5:17 PM, ron minnich wrote: > On Fri, Feb 5, 2010 at 1:29 AM, Stefan Reinauer wrote: > >> On 2/5/10 5:28 AM, Myles Watson wrote: >> >>>> -CONFIG_LOGICAL_CPUS = 0x0 - Why would newconfig specify 0 cpus??? >>>> >>>>

Re: [coreboot] newconfig to Kconfig for Dummies

On 2/5/10 5:28 AM, Myles Watson wrote: >> -CONFIG_LOGICAL_CPUS = 0x0 - Why would newconfig specify 0 cpus??? >> > LOGICAL_CPUS is code for multiple cores. In this case I'm assuming that > your CPU is single-core. Also, despite what the name implies, this is a "boolean" type of value, 0 mean

Re: [coreboot] Safe check method

On 2/4/10 4:44 PM, Krzysztof Walkiewicz wrote: > Hello everybody, > > I have a question: is there any safe method to check if coreboot will > work with my old Toshiba A60-302 laptop? Yes, there is a very safe method: Check the list of supported systems on our web page: http://www.coreboot.org/Sup

Re: [coreboot] M57SLI is not booting successful...

> Harald > Can you do a binary search to find the revision that broke it? -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB

Re: [coreboot] [commit] r5086 - trunk/src/mainboard/gigabyte/m57sli

I think we should modify all boards to use $(obj)/dsdt if they do not. What was the problem without the patch? -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergerich

Re: [coreboot] [PATCH] fix Tyan s2881 boot (Kconfig)

On 2/3/10 6:50 PM, Ward Vandewege wrote: > This fixes breakage introduced in r5051. > > Thanks, > Ward. > > Sorry for the inconvenience. Acked-by: Stefan Reinauer -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 76

[coreboot] [PATCH] (resend to mailing list) COM2 on Geode

See patch. fixup patch from ticket #152 for coreboot trunk (http://tracker.coreboot.org/trac/coreboot/ticket/152) Signed-off-by: Stefan Reinauer Index: src/southbridge/amd/cs5536/cs5536_early_setup.c === --- src/southbridge/amd

Re: [coreboot] [PATCH]: Disable ExtINT in ioapic.c

On 2/2/10 4:25 AM, Bao, Zheng wrote: > Index: src/arch/i386/smp/ioapic.c > === > --- src/arch/i386/smp/ioapic.c(revision 5073) > +++ src/arch/i386/smp/ioapic.c(working copy) > @@ -110,7 +110,7 @@ > #endif > > /

Re: [coreboot] [PATCH] Intel 82830 overhaul

tlog snip below (shows 512MB double sided SO-DIMM in > socket 1 and 64MB single sided onboard memory) and attached patch. > > Signed-off-by: Joseph Smith Nice! Acked-by: Stefan Reinauer -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax:

Re: [coreboot] dell server BIOS setting insanity

other machines. Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE24567486

Re: [coreboot] Tinyscheme ported to coreboot/libpayload

Dear Silvain, On 1/31/10 1:34 PM, Sylvain Ageneau wrote: > Hello, > > I'd like to announce that tinyscheme > can now run as a > coreboot payload. > > TinyScheme is a lightweight Scheme interpreter that implements as > large a subset of R5RS as was poss

[coreboot] It's not just v2 anymore

See patch :-) -- coresystems GmbH . Brahmsstr. 16 . D-79104 Freiburg i. Br. Tel.: +49 761 7668825 . Fax: +49 761 7664613 Email: i...@coresystems.de . http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg . HRB 7656 Geschäftsführer: Stefan Reinauer . Ust-IdNr.: DE245674866

Re: [coreboot] LinuxBIOS V1 ?!

o be taken first. Best regards, Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • U

Re: [coreboot] [PATCHes] mostly Kbuild fixes for out of tree build, Kconfig support in abuild

On 1/29/10 9:16 PM, Myles Watson wrote: > > > * don't turn on WARNINGS_AS_ERRORS for Qemu per default > > > > I disagree with this change. I think it should be noticed when > changes add warnings to a target that is free of them. I think the > goal should be to be able to turn this on for all t

Re: [coreboot] MSC board CXB-A945M

far. It might just be an issue of the right answer to the int15 calls of the VGA OPROM though. Best regards, Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht:

Re: [coreboot] [PATCH] Update LinuxBIOS/coreboot support in memtest86+ 4.0

the same point >> (after 2 sec). >> >> bye and thx, >> Knut Kujat. >> >> Stefan Reinauer escribió: >> >> >>> Knut, >>> >>> are the values the same as with the vendor bios? Do you get any errors >>> at all, or

Re: [coreboot] [PATCH] Update LinuxBIOS/coreboot support in memtest86+ 4.0

> > If you need some more output of whatever just ask me. > > bye and thx, > Knut Kujat > -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Regi

Re: [coreboot] [PATCH]even more kconfig

sc520 systems > > The only difference in UDELAY configuration to newconfig is via/epia > (TSC instead of IO), but given that C3 is shown to support TSC on other > boards, I preferred more regular configurations. > > > Signed-off-by: Patrick Georgi > Acked-by: Stefan

Re: [coreboot] [PATCH]kconfig

rc/mainboard/supermicro/h8dmr_fam10/Kconfig (working copy) > @@ -136,3 +136,8 @@ > bool > default n > depends on BOARD_SUPERMICRO_H8DMR_FAM10 > + > +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID > + hex > + default 0x1511 > + depends on BOARD_SUPERMICRO_H8DMR_FAM10

Re: [coreboot] [PATCH]some more kconfig

; MAX_PHYSICAL_CPUS > ROM_SIZE > TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 > > Signed-off-by: Patrick Georgi > Acked-by: Stefan Reinauer -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Reg

Re: [coreboot] [PATCH] Update LinuxBIOS/coreboot support in memtest86+ 4.0

8825 . Fax: +49 761 7664613 Email: i...@coresystems.de . http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg . HRB 7656 Geschäftsführer: Stefan Reinauer . Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Hint for boot from a PCI device.

On 1/24/10 10:27 AM, v...@ru.ru wrote: > How about debuging/loading/using coreboot from a PCI device? Do you have a pointer to appropriate PCI cards? I guess Robson/TurboMemory cards won't work, will they? Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/lis

Re: [coreboot] [PATCH] Superiotool: Add VT82C686

but you might get lucky. >> >> This adds an additional requirement to superiotool: libpci. I have made >> the PCI code conditional on PCI_SUPPORT for now. >> >> Signed-off-by: Carl-Daniel Hailfinger >> >> > Ping? > I guess nobody has that

[coreboot] [PATCH] Update LinuxBIOS/coreboot support in memtest86 3.5

Registergericht: Amtsgericht Freiburg . HRB 7656 Geschäftsführer: Stefan Reinauer . Ust-IdNr.: DE245674866 diff -ur memtest86-3.5.orig/Makefile memtest86-3.5/Makefile --- memtest86-3.5.orig/Makefile 2009-01-06 07:03:23.0 +0100 +++ memtest86-3.5/Makefile 2010-01-23 16:13:09.0

Re: [coreboot] [PATCH] Update LinuxBIOS/coreboot support in memtest86+ 4.0

On 1/23/10 4:17 PM, Peter Stuge wrote: > Stefan Reinauer wrote: > >> +++ memtest86+-4.00/linuxbios.c 2010-01-23 12:45:06.0 +0100 >> > .. > >> @@ -54,16 +54,16 @@ >> } >> >> #define for_each_lbrec(head, rec) \ >

[coreboot] [PATCH] Update LinuxBIOS/coreboot support in memtest86+ 4.0

tems.de . http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg . HRB 7656 Geschäftsführer: Stefan Reinauer . Ust-IdNr.: DE245674866 diff -urN memtest86+-4.00.orig/Makefile memtest86+-4.00/Makefile --- memtest86+-4.00.orig/Makefile 2009-09-22 02:35:46.0 +0200 +++

Re: [coreboot] Memtest86+ failing on coreboot system.

rd you're using. Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr

Re: [coreboot] Porting to Intel Atom

Compiles fine here with r5039 -- coresystems GmbH . Brahmsstr. 16 . D-79104 Freiburg i. Br. Tel.: +49 761 7668825 . Fax: +49 761 7664613 Email: i...@coresystems.de . http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg . HRB 7656 Geschäftsführer: Stefan Reinauer . Ust-IdNr.: DE2

[coreboot] [PATCH] drop CONFIG_COREBOOT_V2 hack

/ Registergericht: Amtsgericht Freiburg . HRB 7656 Geschäftsführer: Stefan Reinauer . Ust-IdNr.: DE245674866 drop COREBOOT_V2 and COREBOOT_V4 define. We're not sharing code with v3 anymore so this ugly hack is no longer needed. Signed-off-by: Stefan Reinauer Index: src/Kc

[coreboot] [PATCH] Kontron 986LCD-M MP table fixes

See patch -- coresystems GmbH . Brahmsstr. 16 . D-79104 Freiburg i. Br. Tel.: +49 761 7668825 . Fax: +49 761 7664613 Email: i...@coresystems.de . http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg . HRB 7656 Geschäftsführer: Stefan Reinauer . Ust-IdNr.: DE245674866 Kontron

[coreboot] [PATCH] YABEL non-default display support for Kontron 986LCD-M

See patch -- coresystems GmbH . Brahmsstr. 16 . D-79104 Freiburg i. Br. Tel.: +49 761 7668825 . Fax: +49 761 7664613 Email: i...@coresystems.de . http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg . HRB 7656 Geschäftsführer: Stefan Reinauer . Ust-IdNr.: DE245674866 Add

[coreboot] [PATCH] yabel fix after rom_address breakage

See patch -- coresystems GmbH . Brahmsstr. 16 . D-79104 Freiburg i. Br. Tel.: +49 761 7668825 . Fax: +49 761 7664613 Email: i...@coresystems.de . http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg . HRB 7656 Geschäftsführer: Stefan Reinauer . Ust-IdNr.: DE245674866 dev

Re: [coreboot] [PATCH]fix kconfig builds

han > newconfig for a number of boards, but it's more consistent now, as > southbridges usually use the setup_ioapic() function. > > 20100118-3-d945gclf > Make ACPI build on intel/d945gclf > > Signed-off-by: Patrick Georgi > Both are Acked-by: Stefan Reinauer --

[coreboot] [PATCH] libpayload timer function overflow

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

Re: [coreboot] [PATCH] [3/7] Roda RK886EX support: SMSC LPC47N227

oresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] [4/7] Roda RK886EX support: EC Renesas M3885X

> Did they use the Flash or Mask ROM version of the M3885X in the laptop? > > M38857M8-XXXHP 32K 1K Mask ROM 8MHz/3.0 to 3.6V > M38858MC-XXXHP 48K 1.5K Mask ROM 8MHz/3.0 to 3.6V > M38859FFHP 60K 2K Flash memory 8MHz/3.0 to 3.6V > M3885

Re: [coreboot] [PATCH] [3/7] Roda RK886EX support: SMSC LPC47N227

Dear Cristi, > Is this SuperIO chip very different from the generic SMSC ones whose > support code can be found in src/superio/smscsuperio? For avoiding code > duplication it would be nice to move it there if it's not too hard. > Unfortunately, the generic SMSC driver is not suitable, as it assu

Re: [coreboot] [commit] r5025 - trunk/src/northbridge/intel/i945

On 1/17/10 4:45 PM, Joseph Smith wrote: > On 01/17/2010 08:47 AM, s...@coreboot.org wrote: >> Author: stepan >> Date: 2010-01-17 14:47:35 +0100 (Sun, 17 Jan 2010) >> New Revision: 5025 >> >> Modified: >> trunk/src/northbridge/intel/i945/early_init.c >> trunk/src/northbridge/intel/i945/ramin

Re: [coreboot] msrtool: Read both values in diff mode from file [was: coreboot and MSM800BEV]

wed, a space character now ends the MSR value. Any > other character can still be used as separator however, so the following > syntax still works as expected: > > msrtool -i 4c0f=f2f100ff:56960004 > > Signed-off-by: Peter Stuge > Acked-by: Stefan Reinauer > Pre

Re: [coreboot] [PATCH] [7/7] Roda RK886EX support: mainboard and build target

On 1/16/10 9:12 PM, Peter Stuge wrote: > Stefan Reinauer wrote: > >> +++ src/mainboard/roda/rk886ex/Kconfig (revision 0) >> @@ -0,0 +1,62 @@ >> +config BOARD_RODA_RK886EX >> +bool "RK886EX" >> +select ARCH_X86 >> +select CPU_

Re: [coreboot] [ANNOUNCE] Roda RK886EX (Rocky III+) notebook support

On 1/17/10 1:40 AM, Carl-Daniel Hailfinger wrote: > Hi Stefan, > > Absolutely awesome! Congratulations! This is really great news. > > On 16.01.2010 20:09, Stefan Reinauer wrote: > >> I am especially glad to announce that coresystems GmbH is >> releasing corebo

Re: [coreboot] [PATCH] [1/7] Roda RK886EX support: i945 updates

On 1/16/10 8:23 PM, ron minnich wrote: > I'm good with acking the entire series > > Acked-by: Ronald G. Minnich > > Thank you! Committed as revisions r5025-5031. Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH] [6/7] Roda RK886EX support: PCIe tuning

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Initial

[coreboot] [PATCH] [5/7] Roda RK886EX support: Texas Instruments PCI7420

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Add

[coreboot] [PATCH] [4/7] Roda RK886EX support: EC Renesas M3885X

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Add

[coreboot] [PATCH] [3/7] Roda RK886EX support: SMSC LPC47N227

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Add

[coreboot] [PATCH] [2/7] Roda RK886EX support: ICH7 updates

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 ICH7

[coreboot] [PATCH] [1/7] Roda RK886EX support: i945 updates

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Support

[coreboot] [ANNOUNCE] Roda RK886EX (Rocky III+) notebook support

t für Sicherheit in der Informationstechnologie (Federal Office for Information Security, BSI) A big thank you also goes to everyone who worked with coresystems on this project. Best regards, Stefan Reinauer -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825

Re: [coreboot] [1/2] coreboot cleanup: readl -> read32, writel -> write32

Thanks, this went in as r5022. Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: D

Re: [coreboot] [PATCH] ectool - add support for dumping EC index ram

urg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] buildgcc - reference toolchain update

urg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH] buildgcc - reference toolchain update

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Update

[coreboot] [PATCH] ectool - add support for dumping EC index ram

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 ectool

Re: [coreboot] [PATCH] nvramtool output fix

urg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [2/2] coreboot cleanup: generic IOAPIC setup

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 coreboot

[coreboot] [1/2] coreboot cleanup: readl -> read32, writel -> write32

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 coreboot

Re: [coreboot] [commit] r5008 - trunk/util/msrtool

On 1/15/10 8:20 PM, Peter Stuge wrote: > s...@coreboot.org wrote: > >> Support for the AMD Geode GX2 Processors to Msrtool. >> It seems to work as it was tested >> > Please do not accept "it seems to work" for new register > descriptions, always review them against the available > documenta

Re: [coreboot] [MSRTOOL][PATCH] Add Geode GX2 processor support.

On 12/18/09 9:04 PM, Nils wrote: > support for the AMD Geode GX2 > processors to Msrtool. > It seems to work as i tested it on my Wyse Winterm S50. > > Signed-off-by: Nils Jacobs > > Thanks, r5008 and 5009 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listin

Re: [coreboot] coreboot and MSM800BEV

On 1/15/10 12:57 AM, Peter Stuge wrote: > Unfortunately, msrtool is not > currently available as payload, but perhaps coreinfo can be used to > display MSRs? > > (It would be nice to have msrtool diff mode available in coreinfo, > using a file stored in cbfs for comparison!) > I think a diff mo

Re: [coreboot] [PATCH-v2] Repair vsmsetup on GX2

On 1/14/10 11:33 PM, ron minnich wrote: > On Thu, Jan 14, 2010 at 11:44 AM, Stefan Reinauer > wrote: > >> On 1/14/10 8:08 PM, ron minnich wrote: >> >> Acked-by: Ronald G. Minnich >> >> >> >> I'd like to suggest solving this in a

Re: [coreboot] coreboot and MSM800BEV

On 1/14/10 9:34 PM, Piotr Piwko wrote: > 2010/1/14 Stefan Reinauer : > >> It already is included in cache_as_ram_auto.c >> Just add a line >> ram_check(0x, 0x000a); >> at the end of cache_as_ram_main() >> (assuming you use cache as ram) >>

[coreboot] [PATCH] nvramtool output fix

See patch Consider a string with non-printable characters a "bad value". Otherwise nvramtool -a with random cmos contents can mess up your terminal. Signed-off-by: Stefan Reinauer Index: util/nvramtool/nvramtool.c ==

Re: [coreboot] coreboot and MSM800BEV

On 1/14/10 8:45 PM, Piotr Piwko wrote: >> There is a similar function ram_check() in lib/ramtest.c. >> > Yes, but I don't know how I can force a compilation of /lib/ramtest.c > file during building process. > > It already is included in cache_as_ram_auto.c Just add a line ram_check(0x00

Re: [coreboot] [PATCH-v2] Repair vsmsetup on GX2

On 1/14/10 8:08 PM, ron minnich wrote: > Acked-by: Ronald G. Minnich > > I'd like to suggest solving this in a different way if possible. Roughly two objections: Moving coreboot down to 0x4000 is not safe, and we should attempt to fix it living above 1MB. There are two different ways for doin

Re: [coreboot] [PATCH]make emulation/qemu-x86 slightly more standard

t; > Signed-off-by: Patrick Georgi > Acked-by: Stefan Reinauer Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH]AMDHT misbehaves on recent compilers

On 1/7/10 2:41 PM, Kevin O'Connor wrote: > On Thu, Jan 07, 2010 at 10:09:23AM +0100, Stefan Reinauer wrote: > >> On 1/7/10 5:23 AM, Kevin O'Connor wrote: >> >>> I don't think the above is a problem (the pointer foo resides on the >>> sta

Re: [coreboot] coreboot and MSM800BEV

Dear Piotr, Your SPD rom can not be read correctly, hence your RAM controller is not set up correctly... Stefan On 07.01.2010, at 14:22, Piotr Piwko wrote: Hello, I am preparing the coreboot version for MSM800BEV board from Digital Logic. This is the same branch as MSM800SEV board so, I'

Re: [coreboot] [PATCH]AMDHT misbehaves on recent compilers

On 1/7/10 5:23 AM, Kevin O'Connor wrote: > I don't think the above is a problem (the pointer foo resides on the > stack, but the string contents do not). The following is a problem: > > const char foo[]="foobar\n"; > > (both the pointer and the array contents are on the stack), and indeed >

Re: [coreboot] [PATCH]AMDHT misbehaves on recent compilers

On 1/6/10 10:31 PM, Myles Watson wrote: >> arg, that kind of error is almost embarassing :-) >> > This seems like something that could have easily been caught by static > analysis, but I can't find a compiler warning that would have caught it. > > Could scan-build have caught it (I looked and

Re: [coreboot] [PATCH] tinybootblock for AMD K8 and Asus M2V-MX SE

On 1/4/10 11:23 PM, Rudolf Marek wrote: > Hello, > > Thanks to Patrick we have now support for the tiny bootblock for Asus > M2V-MX SE > which has K8 CAR. It was pretty straightforward! > > Signed-off-by: Rudolf Marek Acked-by: Stefan Reinauer -- coresystems GmbH • Br

Re: [coreboot] [PATCH]Kconfig: timers, intel cpus, tinybootblock, kontron 986lcd-m

On 1/4/10 7:06 PM, Patrick Georgi wrote: > Thank you for the ACKs, commited as r4996. > > Here's an updated set of patches which also fixes the udelay issues the > previous set brought up (see below) > > Am 03.01.2010 23:22, schrieb Stefan Reinauer: > >>> 2010

Re: [coreboot] unsuported Motherboard

On 1/4/10 12:17 PM, Joao Mamede wrote: > Hello I want to use coreboot in an old laptop (in order to > replace/upgrade a fried graphics card). > Both the southern and northernbridges are suported > The laptop is the A8js from asus. > > Here's an lspci > 00:00.0 Host bridge: Intel Corporation Mobile

Re: [coreboot] [PATCH]Kconfig: timers, intel cpus, tinybootblock, kontron 986lcd-m

Very nice! On 1/3/10 10:08 PM, Patrick Georgi wrote: > Hi, > > batch of patches: > > 20100103-1-use-selected-udelay-function > Kconfig used the TSC timer unconditionally. > Acked-by: Stefan Reinauer > 20100103-2-include-forgotten-intel-socket > An intel so

[coreboot] [PATCH] cleanup __PRE_RAM__

See patch * Explicitly add __PRE_RAM__ where it should be added. * Don't implicitly add __PRE_RAM__ in romcc. Fixes intel/xe7501devkit Signed-off-by: Stefan Reinauer Index: src/mainboard/axus/tc320/auto.c === --- src/main

Re: [coreboot] Integrated graphics controller on second bus?

On 1/3/10 4:13 PM, Andrej Skirn wrote: > Stefan Reinauer wrote: >> >> Are you building with Kconfig or with "newbuild"? If you are not using >> Kconfig, you have to edit the file Config.lb instead of the file >> devicetree.cb >> >> > Kconfi

Re: [coreboot] Integrated graphics controller on second bus?

664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] arima irq issues

; cable? > [FAILED] > Bringing up interface myri0: > Determining IP information for myri0...RTNETLINK answers: Input/output > error > > Any ideas? Thanks. > -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH]some more kconfig

Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH] HAVE_HIGH_TABLES

Make Kconfig more similar to newconfig: enable "HAVE_HIGH_TABLES" per default. Signed-off-by: Stefan Reinauer Index: src/Kconfig === --- src/Kconfig(revision 4981) +++ src/Kconfig(working copy) @@ -259,7 +259,7 @@

Re: [coreboot] [PATCH] The function int15 running on the Technexion's tim5690.

http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [RFC] CMOS options

lower 128 bytes. Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [RFC] CMOS options

On 12/9/09 8:34 AM, Peter Stuge wrote: > Stefan Reinauer wrote: > >> Many boards have options that make no sense because people love >> copy and paste for that stuff. >> > No, but because people do not understand how it works and what is > required to get a

Re: [coreboot] [RFC] CMOS options

Rudolf Marek wrote: > Hi all, > > Is there someone who is actively using most of the CMOS options? For > example I > just know that Luc is using at least the VRAM size. I think he > mentioned that on > M2V-MX SE memory init options are too dangerous and board won't boot > anymore if > set wrong - m

Re: [coreboot] VIA EDEN ESP (C3) + Apollo CLE266(VT8623) + VT8237R + W83627HG

Andrej Skirn wrote: > Stefan Reinauer wrote: >> On 12/8/09 12:58 AM, Andrej Skirn wrote: >> >> >>> Presently, my main problem seems to be that the >>> northbridge/via/vt8623/raminit.h does not define a mem_controller >>> struct required by the

Re: [coreboot] VIA EDEN ESP (C3) + Apollo CLE266(VT8623) + VT8237R + W83627HG

On 12/8/09 12:58 AM, Andrej Skirn wrote: > Presently, my main problem seems to be that the > northbridge/via/vt8623/raminit.h does not define a mem_controller > struct required by the southbridge code, so the north- and southbridge > code don't seem to be clearly delimited. try completely comment

Re: [coreboot] cbfstool: Fill memory allocated in create_cbfs_file() with 0xff

iprog SF100, but I guess I need to figure out if it does "smart flashing" at all.. (it did with some software release afaicr) Anyways, good idea: Acked-by: Stefan Reinauer Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] i440LX Patch

Maciej Pijanka wrote: > Hello, > > I try to make biostar m6tld running, and created patch for 440lx using 440bx > code as template. > Patch in attachment > > Best regards > Maciej > > Awesome! Committed as r4967... Do you have a mainboard patch to go with it, too? When you say "try" what was

Re: [coreboot] [PATCH]Unify .id section offsets

On 11/27/09 6:42 PM, Carl-Daniel Hailfinger wrote: > To be fair to v3 users, we'd have to merge LAR parsing as well if we > merge CBFS parsing. I don't think there ever was such a group of people. Outside the well-known dozen, at least. Stefan -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] [PATCH] The PC buzzer for TIM-5690.

On 11/23/09 10:58 AM, Uwe Hermann wrote: > On Mon, Nov 23, 2009 at 12:01:26PM +0800, Bao, Zheng wrote: > >> Should the spkr.c be in the folder sb600, or more public folders like >> pc80? >> > It looks generic to me, I'd put it into lib or src/arch/i386/lib as it > might be x86-specific. > >

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