Hi Carl-Daniel,
thanks a lot for bringing this up..
* Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net [120504 00:16]:
coreboot has a requirement to store some data in flash to get some
chipsets to work well. There are multiple ways to achieve this:
1. Write flashing code from
* manasa gv manasa671...@gmail.com [120419 12:54]:
Hi,
I have done patch review of 707 that is to Fix address in Real mode IDT ..
To find this i have gone through Intel IA-32 Vol-3A manual..Here am
using LIDT instruction to fix address in IDT register..I thought
below given code may
On 4/10/12 11:13 PM, Marc Jones wrote:
Stefan, can you explain the requirement or consider how else to only
do this on a processor that requires it?Marc
I will try to reconstruct how this was needed. I might not have the test
system anymore. If it works without now, we should drop that patch
* Patrick Georgi patr...@georgi-clan.de [120406 17:32]:
Am 06.04.2012 17:27, schrieb Marc Jones:
Can you be more descriptive to how it fails? Does it hang on that
instruction?
That change might also break on future CPUs (if they finally manage
to make the TPM stuff secure, so that's a big
* Kyösti Mälkki kyosti.mal...@gmail.com [120404 10:54]:
3. Microcode updates
The tiny bootblock doesn't seem like the correct place for microcode
updates.
As mentioned in one of the reviews, this is needed on many modern CPUs
before entering Cache As Ram.
Stefan
--
coreboot mailing list:
On 4/2/12 3:26 PM, Paul Menzel wrote:
Dear Duncan, dear Stefan,
Am Montag, den 02.04.2012, 22:36 +0200 schrieb Stefan Reinauer:
Stefan Reinauer (stefan.reina...@coreboot.org) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/844
-gerrit
commit
* Julian Shulika herca...@gmail.com [120329 14:28]:
Hi , everyone! Can I use gdb debug tool with coreboot v4.0? This information
is
oudated
coreboot has an easy to use interface to the GNU debugger gdb. To enable it,
add the following two lines to your mainboard's Options.lb:
uses
* Idwer Vollering vid...@gmail.com [120215 17:33]:
Or: how to start a multicore (hyperthreading) processor as if it were
a singlecore (non-hyperthreading) processor.
Would it be necessary to configure APIC/IPI in serialice' mainboard
specific code?
You probably need something like:
* ali hagigat hagigat...@gmail.com [120214 18:48]:
I have initialized Intel 82815 SDRAM controller but for a special type
of RAM without reading SPD registers. I know that DRP register is :
0xCC. I added the code to Coreboot.
I tested much and concluded that RAM has a problem in a way as you
* Software Developer softwaredeveloper...@googlemail.com [120127 12:41]:
Hi,
we're evaluating some bootloaders that we could use for our Intel E6xx with
EG20 platform (its exactly the Kontron nanoETXexpress-TT).
See here: http://us.kontron.com/products/computeronmodules/com+express/
* Daniel Lindenaar daniel-coreb...@lindenaar.eu [120111 15:13]:
I understand what you're saying, yet I've gotten my hands on two
boards with the aforementioned chipsets and a lot of goodies on
them, so I thought to give it a go before spending €€€ for an
already supported board (which would
On 12/31/11 5:00 AM, ali hagigat wrote:
I downloaded the coreboot version 4 for a Ubuntu system. When i want to execute
util/crossgcc/make
It stops complaining that there is an error building GDB!
If i want to make without GDB like by buildgcc, it stops , the error
is that it can not find one h
On 11/22/11 5:20 AM, Kyösti Mälkki wrote:
Hi
Could someone explain the use of boot_cpu() in bootblock_normal.c
main()? I thought only the BSP CPU executes this code (currently)?
I am about to push a change that does early SMP init for hyper-threading
CPUs to allow cache-as-ram implementation.
On Tue, 22 Nov 2011 08:01:01 +0200, Kyösti Mälkki wrote:
On Tue, 2011-11-22 at 06:30 +0900, Stefan Reinauer wrote:
On 11/22/11 5:20 AM, Kyösti Mälkki wrote:
Hi
Could someone explain the use of boot_cpu() in bootblock_normal.c
main()? I thought only the BSP CPU executes this code (currently
On 10/24/11 3:15 AM, Patrick Georgi wrote:
Therefore, I propose (http://review.coreboot.org/#change,320) to get
rid of the big bootblock variant altogether. This might break some
boards (silently: they still build, but they fail on boot), but at
least it forces action to fix them.
* Alp Eren Köse alperenk...@buyutech.com.tr [111018 11:25]:
Hi thanks all for your help,
I have arranged the devicetree.cb as suggested, you can see it at the
attachment.
Put the superio chip under the LPC bridge section, but I didn't get how did
you
know it?
Added those to the
* Alp Eren Köse alperenk...@buyutech.com.tr [111018 17:02]:
By the way I do not have a CMC state machine binary, which it says:
#We don't ship that, but booting without it is bound to fail
in the src/southbridge/intel/sch/Makefile.inc file. What is it, how can get
it?
Is it likely for that
* Marc Jones marcj...@gmail.com [111016 10:10]:
I have created 2 devicetree file :
devicetree_f15.cb for platform with family 15 CPU
devicetree_f10.cb for platform with family 10 CPU
I changed the makefile to create a symbol link “devicetree.cb” link to
* Marc Jones marcj...@gmail.com [111014 06:22]:
On Thu, Oct 13, 2011 at 3:19 AM, She, Kerry kerry@amd.com wrote:
Hello,
Some mainboard support more than one family of CPUs with same socket type,
Such as SuperMicro/h8scm:
* Myles Watson myle...@gmail.com [111012 08:19]:
On Tue, Oct 11, 2011 at 10:13 PM, Oskar Enoksson e...@lysator.liu.se wrote:
I get the following warnings:
APIC: 00 missing read_resources
APIC: 01 missing read_resources
APIC: 02 missing read_resources
APIC: 03 missing read_resources
On 10/10/11 9:02 AM, Alp Eren Köse wrote:
As written on the subject 'make crossgcc' fails as following:
Skipping GDB as requested by command line
Building IASL 20110623 ... failed
make[1]: *** [build-without-gdb] Error 1
make: *** [crossgcc] Error 2
Anyone knows why?
and the
* Pedro Armando Ojeda May pedroojeda2...@googlemail.com [110922 07:08]:
I send you the information requested in the wiki of coreboot.
The chipset is supported, the laptop itself is not.
Please get it working and send a patch! :-)
--
coreboot mailing list: coreboot@coreboot.org
On 8/22/11 1:37 AM, Paul Menzel wrote:
Am Montag, den 22.08.2011, 04:55 +0200 schrieb Alec Ari:
Alec Ari (neotheu...@ymail.com) just uploaded a new patch set to gerrit, which
you can find at http://review.coreboot.org/166
-gerrit
commit d402be72762f60d4b60edf5662d31a14eccb03ec
Author: Alec
* Tadas Slotkus devta...@gmail.com [110811 00:32]:
There will be a problem leaving the XIP area cached while trying to
write to the flash. At the least this means it's not possible to write
the whole flash. Is this intended? What's the plan here?
Should it be possible to map flash
* Dsouza, Malcolm malcolm.dso...@igatepatni.com [110809 14:40]:
Thanks Corey,
1. I agree that before reading through the code, it is better to first check
if the BIOS guides are available. However I would still like the answer to
my question if I wish to carry on with the
On 8/1/11 1:28 PM, Marc Jones wrote:
Tadas,
On Mon, Aug 1, 2011 at 1:08 PM, Tadas Slotkusdevta...@gmail.com wrote:
Hi, thank you both for the answers. I have studied libpci from
libpayload and removed that device list generation with mallocs. Done a
bunch of trial-error cleanup and now
* Hamo hamo...@gmail.com [110726 11:05]:
Hi lists,
As I have moved forward to writing the ramstage, much more problems came out.
PCI devices are just extra devices that can be used but not key
devices like those on X86. Most devices on ARM are connected through
AHBA bus and can be configured
On 7/2/11 2:08 PM, Rudolf Marek wrote:
Hi,
Yes even 486 would be good fit! (It has more closer aligns etc). As
Stefan mentioned, some CPU might not have SSE enabled failing to
execute coreboot. Maybe this is a bit broader problem.
Thanks
Rudolf
Note that this problem does not happen with
On Tue, Jun 21, 2011 at 8:34 PM, Kevin O'Connor ke...@koconnor.net wrote:
On Mon, Jun 20, 2011 at 10:58:06PM -0700, Darren Hart wrote:
On 06/20/2011 04:09 PM, Cristian Măgherușan-Stanciu wrote:
Hi,
I documented the latest developments (git and crossgcc) at
* dove - railing doverail...@gmail.com [110619 14:11]:
I have phoned Australia and spoke to an expert in Procon.com.au about 2 times
and corresponded via email. Procon.com.au are wanting several hundred dollars
whether it's my font or theirs. This is not affordable. I don't know why
vga
Hi Darren,
* Darren Hart dvh...@linux.intel.com [110621 00:19]:
I'm new to coreboot and just trying to get it to boot into qemu. I've
tried using SeaBios as well as just copying yes to payload.elf. I
updated the Makefile to use gcc 4.5 instead of the 4.4 that ships with
my distribution
* repository service s...@coreboot.org [110604 17:44]:
Author: stuge
Date: Sat Jun 4 17:44:31 2011
New Revision: 6625
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6625
Modified: trunk/src/mainboard/asrock/e350m1/romstage.c
* repository service s...@coreboot.org [110604 17:44]:
Author: stuge
Date: Sat Jun 4 17:44:54 2011
New Revision: 6626
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6626
Log:
Port persimmon r6583 to e350m1: pstate 0 early
Switch processor cores to pstate 0 early to reduce
* repository service s...@coreboot.org [110604 17:45]:
Author: stuge
Date: Sat Jun 4 17:45:12 2011
New Revision: 6627
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6627
Log:
Port persimmon r6584 and r6601 to e350m1: SPI prefetch early
Enable SPI cacheline prefetch early to
* repository service s...@coreboot.org [110604 17:47]:
Author: stuge
Date: Sat Jun 4 17:47:05 2011
New Revision: 6633
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6633
Log:
Port persimmon r6591 to e350m1: ROM cache early
Enable rom cache early to reduce boot time.
* Peter Stuge pe...@stuge.se [110604 18:16]:
Stefan Reinauer wrote:
+++ trunk/src/mainboard/asrock/e350m1/romstage.c Sat Jun 4 17:44:31
2011(r6625)
..
+__outdword (0xcf8, 0x8000a3a0);
what's the reason to not use pci_read_config32() here?
+++ trunk/src
* Peter Stuge pe...@stuge.se [110604 18:19]:
Stefan Reinauer wrote:
+++ trunk/src/mainboard/asrock/e350m1/romstage.c Sat Jun 4 17:45:12
2011(r6627)
@@ -50,6 +50,13 @@
// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot
time
__writemsr
On 6/4/11 3:22 PM, dove - railing wrote:
I am not a techie.
Would it be correct to say that fonts at the Bios level are decided by
the Video card / VGA firmware?
The VGA BIOS loads the initial font.
Is there an opensource utility for them?
I found this, it's not open source though:
On 6/4/11 10:47 AM, Sven Schnelle wrote:
motherboards can use this hook to get notified if someone writes
to the APM_CNT port (0xb2). If the hook returns 1, the chipset
specific hook is also skipped.
Signed-off-by: Sven Schnellesv...@stackframe.org
Acked-by: Stefan Reinauer stefan.reina
and there are no event queue registers in the EC register space,
we're using 0x62/0x66 as EC I/O ports as long as ACPI is disabled.
Signed-off-by: Sven Schnellesv...@stackframe.org
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org
* Thomas Rohloff v10la...@myway.de [110603 12:33]:
Am Thu, 02 Jun 2011 06:37:16 -0700
schrieb Stefan Reinauer stefan.reina...@coreboot.org:
On 6/1/11 10:52 PM, Thomas Rohloff wrote:
Hi,
I have a AsRock 870 Etreme3
( http://www.asrock.com/mb/overview.asp?model=870%20extreme3
On 6/1/11 10:52 PM, Thomas Rohloff wrote:
Hi,
I have a AsRock 870 Etreme3
( http://www.asrock.com/mb/overview.asp?model=870%20extreme3 ) and
wanted to know if it's supported b coreboot.
See http://www.coreboot.org/Supported_Motherboards for a list of
supported boards.
So, is this possible?
* Jonathan A. Kollasch jakll...@kollasch.net [110525 18:59]:
+ If (LEqual (Arg0, 8)) {
white spaces look messed up
No, that was intentional, i wanted the LEqual to line up,
though then I didn't pad the single character numbers ...
Sorry not sure what you were trying to achieve. As
* Joe Holden li...@rewt.org.uk [110601 22:29]:
Hi guys,
Not sure if this is the right place to ask, but what are the chances
of the above board being supported?
I have a couple in use and they look like pretty standard ICH7/945
boards: http://www.mini-itx.com/store/?c=47#jnc92-330
Slight
On 5/29/11 4:44 PM, Raleigh Boulware wrote:
Is there a good link to this tool chain?
There are no prebuilt binaries for this tool chain. Type 'make crossgcc'
in coreboot, as suggested several times before in this thread;-)
Stefan
Date: Sun, 29 May 2011 20:05:47 +0300
From:
On 5/29/11 6:06 PM, Gregg Levine wrote:
Hello!
Group I returned from vacation, (which is where SVN worked) on the
Friday. Today I went ahead and attempted the regular and routine
update of SVN. Stefan is it possible, however unlikely that something
where you are located happens to be blocking
* shawn Bai programas...@hotmail.com [110522 06:28]:
Hi,folks,
I searched for 'acpi_tables.c' in directory 'mainboard', and 49
entries come.They are as follows, but not all listed here,just for
your reference.
[..]
I don't know ACPI and don't know the reason why there are so many
files
Did you check the output file? In my tests a .align 4 aligned to 4 bytes not
16.
Sent from my mobile phone
On 22.05.2011, at 19:18, Scott Duplichan sc...@notabs.org wrote:
Stefan Reinauer wrote:
] +.align 4
] Shouldn't this be .align 16 then?
] The as(1) info page says it's in bits
* Jonathan A. Kollasch jakll...@kollasch.net [110523 12:52]:
On Sun, May 22, 2011 at 12:25:37PM -0700, Stefan Reinauer wrote:
On 5/22/11 8:39 AM, repository service wrote:
Author: jakllsch
Date: Sun May 22 17:39:25 2011
New Revision: 6608
URL: https://tracker.coreboot.org/trac/coreboot
* Jonathan A. Kollasch jakll...@kollasch.net [110523 21:28]:
Add ACPI automatic PIC/APIC interrupt routing logic for ck804.
Signed-off-by: Jonathan Kollasch jakll...@kollasch.net
Index: src/southbridge/nvidia/ck804/acpi/ck804.asl
On 5/22/11 8:39 AM, repository service wrote:
Author: jakllsch
Date: Sun May 22 17:39:25 2011
New Revision: 6608
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6608
Log:
Ensure ck804 romstrap is 16-byte aligned.
This alignment seems to be necessary for the chip to recognize it.
On 5/22/11 8:12 AM, Jonathan A. Kollasch wrote:
Optionally treat ck804 memory-mapped PCI configuration space window as a
resource. Not enabled by default because the resource should be
non-posted and there's no way to express that to the resource allocator.
Signed-off-by: Jonathan
On 5/22/11 1:02 PM, Jonathan A. Kollasch wrote:
On Sun, May 22, 2011 at 12:25:37PM -0700, Stefan Reinauer wrote:
On 5/22/11 8:39 AM, repository service wrote:
Author: jakllsch
Date: Sun May 22 17:39:25 2011
New Revision: 6608
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6608
Log
On 5/22/11 1:07 PM, Jonathan A. Kollasch wrote:
On Sun, May 22, 2011 at 12:28:41PM -0700, Stefan Reinauer wrote:
On 5/22/11 8:12 AM, Jonathan A. Kollasch wrote:
Optionally treat ck804 memory-mapped PCI configuration space window as a
resource. Not enabled by default because the resource
On 5/20/11 2:03 AM, Paul Menzel wrote:
Dear coreboot folks,
not knowing who would want to travel to the USA or through the USA, I am
forwarding Lennart’s message to the list.
Stefan, Peter, Ron, Scott, Marc, Rudolf, Sven, Patrick and everyone I
forgot, it would be great if some of you could
* Patrick Georgi patrick.geo...@secunet.com [110520 13:54]:
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
---
Makefile.inc |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
--
coreboot mailing list: coreboot
* Patrick Georgi patrick.geo...@secunet.com [110520 13:54]:
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
* Patrick Georgi patrick.geo...@secunet.com [110520 13:54]:
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
---
Makefile |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
--
coreboot mailing list: coreboot
Alright, I just put in a place holder for a coreboot talk. If there is
interest in a specific topic, please let me know. Otherwise it might be
a mix of a general overview, ACPI, and security
Stefan
* Lennart Poettering lenn...@poettering.net [110520 18:16]:
On Fri, 20.05.11 08:36, Stefan
this accidently went to the coreboot-announce list, resending.
Original Message
Subject:Is there anything I can do to make coreboot better?
Date: Wed, 18 May 2011 14:31:53 +
From: shawn Bai programas...@hotmail.com
To: coreboot-annou...@coresystems.de
* Vikram Narayanan vikram...@gmail.com [110517 16:50]:
On Tue, May 17, 2011 at 4:06 PM, Anders Jenbo and...@jenbo.dk wrote:
Den 17-05-2011 10:41, Андрей Клаус skrev:
Hello everybody,
I'm thinking about porting coreboot to my motherboard (epox 9NPA3I / 9NPA3J
/ 9NPAJ-3 / 9NPA3 Ultra
On 5/18/11 3:21 PM, Peter Stuge wrote:
Paul Menzel wrote:
Can `acpi_tables.c` be shared between certain families or even all
new boards?
If yes, maybe that could be put on a todo list.
Yeah, I ranted about this a bit on IRC. Will take a look in Prague.
I read a nice quote today:
Why rant
On 5/15/11 4:52 PM, Peter Stuge wrote:
repository service wrote:
Log:
Enable rom cache early to reduce boot time.
+++ trunk/src/mainboard/amd/persimmon/romstage.cMon May 16 00:06:09
2011(r6591)
@@ -47,6 +47,11 @@
u32 val;
u8 reg8;
+ // all cores: allow caching of
On 5/15/11 3:57 PM, Peter Stuge wrote:
repository service wrote:
+++ trunk/src/mainboard/amd/persimmon/romstage.cSun May 15 23:54:04
2011(r6584)
..
+ // early enable of PrefetchEnSPIFromHost
+ if (boot_cpu())
+{
+__outdword (0xcf8, 0x8000a3b8);
+__outdword
On 5/14/11 3:17 AM, Prakash Punnoor wrote:
Are you sure? I didn't try it yet, but according to
http://www.spinics.net/lists/linux-usb/msg32912.html
it should be possible to use a Linux machine as USB debug port device.
It might work if your controller has a USB device port. A USB host port
On 5/13/11 5:07 PM, Peter Stuge wrote:
Yogev Ezra wrote:
2. Compulab Fit-PC2 nettop (Intel Atom Z510 / Z530 CPU + US15W chipset).
This however is a rather advanced platform.
coreboot supports none of the components on these platforms.
Actually there is support for the CPU and chipset in
On 5/13/11 8:57 AM, Thomas JOURDAN wrote:
I'm trying to get Windows 7 booting on my Intel Eagle Heights
evaluation board. I tried to follow all the ACPI tips to get Window$
to boot but I can't figure out the bug I'm facing. I'm using a checked
build version of Win 7 64-bits. When I start the
, somedefault)
to
read_option(foo, somedefault)
Signed-off-by: Patrick Georgi patr...@georgi-clan.de
[PATCH] Hide CMOS_VSTART_ and CMOS_VLEN_ prefixes for read_option() use
Signed-off-by: Patrick Georgi patr...@georgi-clan.de
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
---
src
?
Add strlcpy from OpenBSD
Signed-off-by: Patrick Georgi patr...@georgi-clan.de
This one is
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
* Patrick Georgi patr...@georgi-clan.de [110510 23:07]:
Am 10.05.2011 00:17, schrieb Stefan Reinauer:
Looking for drivers/generic/generic in the source code, we use it quite
a lot:
Should we drop all those sub trees? Or try to fix them? What is needed
to fix them?
Fix what
* Patrick Georgi patr...@georgi-clan.de [110510 23:55]:
Am 10.05.2011 22:07, schrieb Stefan Reinauer:
Signed-off-by: Patrick Georgi patr...@georgi-clan.de
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
r6565, thanks.
thanks.
But yes, there aren't any more read_option uses
* Vikram Narayanan vikram...@gmail.com [110510 20:10]:
Hi,
I am using a DELL laptop. The superio used is
Found Nuvoton WPCE775x / NPCE781x (id=0x03, rev=0x06) at 0x4e.
Now the thing is there are no serial ports exposed outside in my laptop.
Is there any other way out to see the debug
* Rudolf Marek r.ma...@assembler.cz [110509 08:34]:
* implement a gdb stub for coreboot
Why not use the one that is there?
Yep, but it seems it does not use HW debugging features like HW
watchpoints. Anyway this was just an idea.
Ah this sounds great. Just wanted to make sure you didn't
Hi,
Looking for drivers/generic/generic in the source code, we use it quite
a lot:
grep generic.generic src/mainboard/*/*/devicetree.cb |wc -l
391
However:
ls src/drivers/generic/
Kconfig Makefile.inc debug
It does not exist.
Should we drop all those sub trees? Or try to fix them? What is
On 5/9/11 4:20 PM, Graeme Russ wrote:
Again, probably a missunderstanding of coreboot on my behalf - U-Boot has
a REALLY primative BIOS implementation (just enough to trick Linux into
booting in an embedded environment). It is basically just some empty VGA
stubs and simple e820 support.
Why
On 5/9/11 5:53 PM, Graeme Russ wrote:
Yes. The information is published by coreboot in the coreboot table
AKA cbtable. libpayload already has code to find it.
Hmm - I don't think linking U-Boot against libpayload is the right
solution. U-Boot is designed to be the primary bootloader
much like
On 5/9/11 6:15 PM, Peter Stuge wrote:
Graeme Russ wrote:
U-Boot is build with the target address in Flash. It initialises memory
and copies itself into RAM at an address calculated by the RAM init code.
Here there should probably be a second possible entry point, for when
U-Boot is a coreboot
On 5/9/11 7:18 PM, Graeme Russ wrote:
On Tue, May 10, 2011 at 11:15 AM, Peter Stugepe...@stuge.se wrote:
Graeme Russ wrote:
My point being that U-Boot needs to know about the arrangement of
memory of the target board.
Yes. The information is published by coreboot in the coreboot table
AKA
On 5/8/11 10:37 PM, Rudolf Marek wrote:
* implement a gdb stub for coreboot
Why not use the one that is there?
--
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http://www.coreboot.org/mailman/listinfo/coreboot
On 5/7/11 12:05 PM, Kevin O'Connor wrote:
On Sat, May 07, 2011 at 08:48:45PM +0200, Sven Schnelle wrote:
Kevin O'Connorke...@koconnor.net writes:
Do you know how long it takes for your keyboard to become responsive?
(You can pass -n to tools/readserial.py to have it report wall times
instead
On 5/7/11 12:05 PM, Kevin O'Connor wrote:
On Sat, May 07, 2011 at 08:48:45PM +0200, Sven Schnelle wrote:
Kevin O'Connorke...@koconnor.net writes:
Do you know how long it takes for your keyboard to become responsive?
(You can pass -n to tools/readserial.py to have it report wall times
instead
On 03.05.2011, at 06:04, Peter Stuge pe...@stuge.se wrote:
repository service wrote:
+++ trunk/src/southbridge/intel/i82801gx/KconfigTue May 3 09:55:30 2011
(r6553)
@@ -38,5 +38,10 @@
int
default 1
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+string
+default
On 03.05.2011, at 11:01, Patrick Georgi patr...@georgi-clan.de wrote:
Am 03.05.2011 18:10, schrieb Stefan Reinauer:
I agree this belongs in the Makefiles.. Not sure why we chose to put it here
but it might have required another makefile pass otherwise
Back then the build system was a bit
* Sven Schnelle sv...@stackframe.org [110503 10:23]:
Hi Paul,
Paul Menzel paulepan...@users.sourceforge.net writes:
Am Dienstag, den 03.05.2011, 09:55 +0200 schrieb repository service:
Author: svens
Date: Tue May 3 09:55:43 2011
New Revision: 6554
URL:
* Sven Schnelle sv...@stackframe.org [110503 21:41]:
Stefan Reinauer stefan.reina...@coreboot.org writes:
Can you do a new analysis on where the boot time goes now? It would be
nice to see if there are more optimizations we can do...
Will do. But right now i have the problem
* Sven Schnelle sv...@stackframe.org [110502 16:13]:
Add an option to make compression of ramstage configurable. Right now
it is always compressed. On my Thinkpad, the complete boot to grub takes
4s, with around 1s required for decompressing ramstage. This is probably
caused by the fact the
* Eric W. Biederman ebied...@xmission.com [110502 22:00]:
Sven Schnelle sv...@stackframe.org writes:
Add an option to make compression of ramstage configurable. Right now
it is always compressed. On my Thinkpad, the complete boot to grub takes
4s, with around 1s required for decompressing
* Stefan Reinauer stefan.reina...@coreboot.org [110502 20:34]:
* Sven Schnelle sv...@stackframe.org [110502 16:13]:
Add an option to make compression of ramstage configurable. Right now
it is always compressed. On my Thinkpad, the complete boot to grub takes
4s, with around 1s required
* Eric W. Biederman ebied...@xmission.com [110503 01:26]:
Was that a destination hard code? The code itself should come out of
the last couple of megabytes before 4G.
Yes. Only the lower 1MB of the destination memory was cached, while
coreboot's ram stage is now copied to 1MB.
My other mail
On 4/28/11 8:01 PM, Scott Duplichan wrote:
Adds a kconfig option to enable gcc link time optimization.
Link time optimization reduces both rom stage and ram stage
image size by removing unused functions and data. Reducing the
image size saves boot time by minimizing the flash memory read
and
* Thom Lauret diracsh...@gmail.com [110427 17:05]:
Hey all,
I know the Sun Ultra 40 has a coreboot image available but is anyone
working on the Sun Ultra 40 M2 ?
You will have to make a new port. Give it a try and let us know how it goes.
Thanks,
Stefan
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On 26.04.2011, at 07:40, Den nis dnns...@gmail.com wrote:
Hi,
Im trying to port the iwave RainbowG6 coreboot code to a platform with the
same CPU (Intel Atom Z530) and chipset (Intel US15W), 1GB RAM (2 ranks, 1024
Mbits device density, x16 device width) and a winbond WPCN381U superio
* Patrick Georgi patr...@georgi-clan.de [110426 16:41]:
Am 26.04.2011 15:59, schrieb Marc Jones:
We found this with some testing at BTDC. This patch sets max freq
defaults for ddr2 and ddr3for fam10. It may be overridden by a
developer setting it in romstage.c.
Please find a better place
On 25.04.2011, at 03:07, Paulo Alexandre A.P. de Oliveira
paulopeixotoolive...@gmail.com wrote:
Hi guys,
I'd like to make a question:
Is Toshiba NB305 netbook supported by coreboot?
No.
Stefan
If so what bios flashing
program should i use? Flash Rom or the manufacturer proprietary one?
* Антон Кочков anton.koch...@gmail.com [110423 06:55]:
Hello!
I'm trying to build coreboot with Clang/LLVM. Why?
Because Clang produce nice error/warning messages, which help find a bugs.
Here will be discussion about such things.
Attached first log:
ROMCC
* Stefan Reinauer stefan.reina...@coreboot.org [110416 02:11]:
* Stefan Reinauer stefan.reina...@coreboot.org [110414 23:46]:
See patch
- include usbdebug.c where appropriate
- don't do ne2k_transmit()s without actual output
Signed-off-by: Stefan Reinauer stefan.reina
This should allow to get rid of a hack when running u-boot as a coreboot
payload.
Stefan
Initialize i8259 in the i82371eb southbridge (isa/lpc) code.
All southbridges should do this, yet almost none do.
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
diff --git a/src/southbridge
* Peter Stuge pe...@stuge.se [110425 22:48]:
Антон Кочков wrote:
ROMCC mainboard/emulation/qemu-x86/bootblock.inc
clang -m32 -MM -MTbuild/mainboard/emulation/qemu-x86/bootblock.inc \
I don't believe you can replace romcc with clang.
This is just the dependency run failing. We
* She, Kerry kerry@amd.com [110422 05:08]:
Hello,
ADVANSUS a785e-i Mainboard support
RS880(RS785E)+SB820 platform
Signed-off-by: Kerry She kerry@amd.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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http
* She, Kerry kerry@amd.com [110422 05:12]:
Signed-off-by: Kerry She kerry@amd.com
SB800 CIMX code can share the AGESA V5 lib code,
some platform only use sb800 cimx code, not use AGESA v5 code,
compile the sb800 cimx and AGESA v5 lib code.
Signed-off-by: Kerry She
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