. Should we back it out until we have
CAR ready?
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: [EMAIL PROTECTED] • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan R
e asm volatile (" jmp 0xADDR;\n");
Stefan
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: [EMAIL PROTECTED] • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer
ron minnich wrote:
> On Wed, Sep 10, 2008 at 1:37 PM, Stefan Reinauer <[EMAIL PROTECTED]> wrote:
>
>
>> Just curious:
>> Why would you say packed is asking for trouble?
>>
>>
>
> it's actually burned me in the past, but I am fine with
wn in local recipient table
Alex, can you read this?
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: [EMAIL PROTECTED] • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan
with their ideas now?
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: [EMAIL PROTECTED] • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE24567
7664613
Email: [EMAIL PROTECTED] • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
7668825 • Fax: +49 761 7664613
Email: [EMAIL PROTECTED] • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
ult configuration for all platforms (for now), so
> remove the previous configurations and infrastructure.
>
> Signed-off-by: Jordan Crouse <[EMAIL PROTECTED]>
>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. B
• HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Peter Stuge wrote:
> Stefan Reinauer wrote:
>
>>> evaluating all current disklabel schemes
>>>
>> I still like Amiga's Rigid Disk Label best. It stores the
>> firmware's filesystem driver for each file in the "partition table"
>
re
> that makes the emulator less picky.
Do you have a log file?
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: [EMAIL PROTECTED] • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäf
761 7668825 • Fax: +49 761 7664613
Email: [EMAIL PROTECTED] • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
sstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: [EMAIL PROTECTED] • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
--
coreboot mailing list: coreboot@coreboot.org
ht
[EMAIL PROTECTED] • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
See patch.
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: [EMAIL PROTECTED] • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
This
See patch
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: [EMAIL PROTECTED] • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
The
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: [EMAIL PROTECTED] • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
ron minnich wrote:
> attached. Builds fine on ubuntu.
>
> ron
>
Sweet.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fa
at for each character.
I vote in favor of dropping my first patch and use Patricks much better
version.
Stefan
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: [EMAIL PROTECTED] • http://www.coresystems.de/
Registerger
Slightly updated, to cursor keys on keyboard work, too. (just some
> cut-off because of putting a short into a char)
> Tested in qemu, both console and serial.
>
>
> Patrick Georgi
>
I'd say Acked-by: Stefan Reinauer <[EMAIL PROTECTED]> but let's wait
for Jor
See patch
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: [EMAIL PROTECTED] • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
After
* Sven Schnelle [110502 16:13]:
> Add an option to make compression of ramstage configurable. Right now
> it is always compressed. On my Thinkpad, the complete boot to grub takes
> 4s, with around 1s required for decompressing ramstage. This is probably
> caused by the fact the decompression does
* Eric W. Biederman [110502 22:00]:
> Sven Schnelle writes:
>
> > Add an option to make compression of ramstage configurable. Right now
> > it is always compressed. On my Thinkpad, the complete boot to grub takes
> > 4s, with around 1s required for decompressing ramstage. This is probably
> > ca
* Stefan Reinauer [110502 20:34]:
> * Sven Schnelle [110502 16:13]:
> > Add an option to make compression of ramstage configurable. Right now
> > it is always compressed. On my Thinkpad, the complete boot to grub takes
> > 4s, with around 1s required for decompressing ramst
* Eric W. Biederman [110503 01:26]:
> Was that a destination hard code? The code itself should come out of
> the last couple of megabytes before 4G.
Yes. Only the lower 1MB of the destination memory was cached, while
coreboot's ram stage is now copied to 1MB.
My other mail to the list shows ho
On 03.05.2011, at 06:04, Peter Stuge wrote:
> repository service wrote:
>> +++ trunk/src/southbridge/intel/i82801gx/KconfigTue May 3 09:55:30 2011
>>(r6553)
>> @@ -38,5 +38,10 @@
>>int
>>default 1
>>
>> +config BOOTBLOCK_SOUTHBRIDGE_INIT
>> +string
>> +default "so
On 03.05.2011, at 11:01, Patrick Georgi wrote:
> Am 03.05.2011 18:10, schrieb Stefan Reinauer:
>> I agree this belongs in the Makefiles.. Not sure why we chose to put it here
>> but it might have required another makefile pass otherwise
> "Back then" the build
* Sven Schnelle [110503 10:23]:
> Hi Paul,
>
> Paul Menzel writes:
>
> > Am Dienstag, den 03.05.2011, 09:55 +0200 schrieb repository service:
> >> Author: svens
> >> Date: Tue May 3 09:55:43 2011
> >> New Revision: 6554
> >> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6554
> >>
* Sven Schnelle [110503 21:41]:
> Stefan Reinauer writes:
> > Can you do a new analysis on where the boot time goes now? It would be
> > nice to see if there are more optimizations we can do...
>
> Will do. But right now i have the problem that the Keyboard isn
On 5/7/11 12:05 PM, Kevin O'Connor wrote:
On Sat, May 07, 2011 at 08:48:45PM +0200, Sven Schnelle wrote:
Kevin O'Connor writes:
Do you know how long it takes for your keyboard to become responsive?
(You can pass "-n" to tools/readserial.py to have it report wall times
instead of adjusted times
On 5/7/11 12:05 PM, Kevin O'Connor wrote:
On Sat, May 07, 2011 at 08:48:45PM +0200, Sven Schnelle wrote:
Kevin O'Connor writes:
Do you know how long it takes for your keyboard to become responsive?
(You can pass "-n" to tools/readserial.py to have it report wall times
instead of adjusted times
On 5/8/11 10:37 PM, Rudolf Marek wrote:
* implement a gdb stub for coreboot
Why not use the one that is there?
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
* Rudolf Marek [110509 08:34]:
> >>* implement a gdb stub for coreboot
> >Why not use the one that is there?
>
> Yep, but it seems it does not use HW debugging features like HW
> watchpoints. Anyway this was just an idea.
Ah this sounds great. Just wanted to make sure you didn't miss that
there
Hi,
Looking for drivers/generic/generic in the source code, we use it quite
a lot:
grep generic.generic src/mainboard/*/*/devicetree.cb |wc -l
391
However:
ls src/drivers/generic/
Kconfig Makefile.inc debug
It does not exist.
Should we drop all those sub trees? Or try to fix them? What is
On 5/9/11 4:20 PM, Graeme Russ wrote:
Again, probably a missunderstanding of coreboot on my behalf - U-Boot has
a REALLY primative BIOS implementation (just enough to trick Linux into
booting in an embedded environment). It is basically just some empty VGA
stubs and simple e820 support.
Why don't
On 5/9/11 5:53 PM, Graeme Russ wrote:
Yes. The information is published by coreboot in the "coreboot table"
AKA cbtable. libpayload already has code to find it.
Hmm - I don't think linking U-Boot against libpayload is the right
solution. U-Boot is designed to be the primary bootloader
much like
On 5/9/11 6:15 PM, Peter Stuge wrote:
Graeme Russ wrote:
U-Boot is build with the target address in Flash. It initialises memory
and copies itself into RAM at an address calculated by the RAM init code.
Here there should probably be a second possible entry point, for when
U-Boot is a coreboot p
On 5/9/11 7:18 PM, Graeme Russ wrote:
On Tue, May 10, 2011 at 11:15 AM, Peter Stuge wrote:
Graeme Russ wrote:
My point being that U-Boot needs to know about the arrangement of
memory of the target board.
Yes. The information is published by coreboot in the "coreboot table"
AKA cbtable. libpay
LEN_foo, somedefault)
> to
> read_option(foo, somedefault)
>
>
> Signed-off-by: Patrick Georgi
> [PATCH] Hide CMOS_VSTART_ and CMOS_VLEN_ prefixes for read_option() use
>
> Signed-off-by: Patrick Georgi
Acked-by: Stefan Reinauer
> ---
> src/cpu/amd/dualcore/d
filter* pf)
> pf->device = -1;
> }
>
> +static char *invalid_pci_device_string = (char*)"invalid pci device string";
minor nitpick, i think this should be (char *), like char *invalid_
earlier in the line. And maybe it can be const?
> Add strlcpy from OpenBSD
>
> Signed-off-by: Patrick Georgi
This one is
Acked-by: Stefan Reinauer
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
* Patrick Georgi [110510 23:07]:
> Am 10.05.2011 00:17, schrieb Stefan Reinauer:
> > Looking for drivers/generic/generic in the source code, we use it quite
> > a lot:
>
> > Should we drop all those sub trees? Or try to fix them? What is needed
> > to fix them?
&
* Patrick Georgi [110510 23:55]:
> Am 10.05.2011 22:07, schrieb Stefan Reinauer:
> >> Signed-off-by: Patrick Georgi
> > Acked-by: Stefan Reinauer
> r6565, thanks.
thanks.
> But yes, there aren't any more read_option uses. Probably a sign that
> the nvram sub
* Vikram Narayanan [110510 20:10]:
> Hi,
>
> I am using a DELL laptop. The superio used is
> "Found Nuvoton WPCE775x / NPCE781x (id=0x03, rev=0x06) at 0x4e".
>
> Now the thing is there are no serial ports exposed outside in my laptop.
> Is there any other way out to see the debug messages of c
On 5/13/11 5:07 PM, Peter Stuge wrote:
Yogev Ezra wrote:
2. Compulab Fit-PC2 nettop (Intel Atom Z510 / Z530 CPU + US15W chipset).
This however is a rather advanced platform.
coreboot supports none of the components on these platforms.
Actually there is support for the CPU and chipset in core
On 5/13/11 8:57 AM, Thomas JOURDAN wrote:
I'm trying to get Windows 7 booting on my Intel Eagle Heights
evaluation board. I tried to follow all the ACPI tips to get Window$
to boot but I can't figure out the bug I'm facing. I'm using a checked
build version of Win 7 64-bits. When I start the in
On 5/14/11 3:17 AM, Prakash Punnoor wrote:
Are you sure? I didn't try it yet, but according to
http://www.spinics.net/lists/linux-usb/msg32912.html
it should be possible to use a Linux machine as USB debug port device.
It might work if your controller has a USB device port. A USB host port
won't
On 5/15/11 4:52 PM, Peter Stuge wrote:
repository service wrote:
Log:
Enable rom cache early to reduce boot time.
+++ trunk/src/mainboard/amd/persimmon/romstage.cMon May 16 00:06:09
2011(r6591)
@@ -47,6 +47,11 @@
u32 val;
u8 reg8;
+ // all cores: allow caching of flash
On 5/15/11 3:57 PM, Peter Stuge wrote:
repository service wrote:
+++ trunk/src/mainboard/amd/persimmon/romstage.cSun May 15 23:54:04
2011(r6584)
..
+ // early enable of PrefetchEnSPIFromHost
+ if (boot_cpu())
+{
+__outdword (0xcf8, 0x8000a3b8);
+__outdword (0xcfc
this accidently went to the coreboot-announce list, resending.
Original Message
Subject:Is there anything I can do to make coreboot better?
Date: Wed, 18 May 2011 14:31:53 +
From: shawn Bai
To:
Hello, guys,
I am very pleased to have the chance to talk wi
* Vikram Narayanan [110517 16:50]:
> On Tue, May 17, 2011 at 4:06 PM, Anders Jenbo wrote:
> > Den 17-05-2011 10:41, Андрей Клаус skrev:
> >
> > Hello everybody,
> >
> > I'm thinking about porting coreboot to my motherboard (epox 9NPA3I / 9NPA3J
> > / 9NPAJ-3 / 9NPA3 Ultra Series). My chipset (CK8
On 5/18/11 3:21 PM, Peter Stuge wrote:
Paul Menzel wrote:
Can `acpi_tables.c` be shared between certain families or even all
new boards?
If yes, maybe that could be put on a todo list.
Yeah, I ranted about this a bit on IRC. Will take a look in Prague.
I read a nice quote today:
"Why rant w
On 5/18/11 7:49 PM, Vikram Narayanan wrote:
What should be done to get the debug messages via an USB-serial.?
For USB-serial adapters you need a full blown USB stack. By the time you
get that up and running, you basically don't need debugging anymore.
Stefan
--
coreboot mailing list: corebo
On 5/20/11 2:03 AM, Paul Menzel wrote:
Dear coreboot folks,
not knowing who would want to travel to the USA or through the USA, I am
forwarding Lennart’s message to the list.
Stefan, Peter, Ron, Scott, Marc, Rudolf, Sven, Patrick and everyone I
forgot, it would be great if some of you could ma
* Patrick Georgi [110520 13:54]:
>
> Signed-off-by: Patrick Georgi
Acked-by: Stefan Reinauer
> ---
> Makefile.inc |2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
* Patrick Georgi [110520 13:54]:
>
> Signed-off-by: Patrick Georgi
Acked-by: Stefan Reinauer
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
* Patrick Georgi [110520 13:54]:
>
> Signed-off-by: Patrick Georgi
> ---
> Makefile |2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
Acked-by: Stefan Reinauer
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Alright, I just put in a place holder for a coreboot talk. If there is
interest in a specific topic, please let me know. Otherwise it might be
a mix of a general overview, ACPI, and security
Stefan
* Lennart Poettering [110520 18:16]:
> On Fri, 20.05.11 08:36, Stefan Reinauer (stefan.re
On 5/22/11 8:39 AM, repository service wrote:
Author: jakllsch
Date: Sun May 22 17:39:25 2011
New Revision: 6608
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6608
Log:
Ensure ck804 romstrap is 16-byte aligned.
This alignment seems to be necessary for the chip to recognize it.
Signe
On 5/22/11 8:12 AM, Jonathan A. Kollasch wrote:
Optionally treat ck804 memory-mapped PCI configuration space window as a
resource. Not enabled by default because the resource should be
non-posted and there's no way to express that to the resource allocator.
Signed-off-by: Jonathan Kollasch
Plea
On 5/22/11 1:02 PM, Jonathan A. Kollasch wrote:
On Sun, May 22, 2011 at 12:25:37PM -0700, Stefan Reinauer wrote:
On 5/22/11 8:39 AM, repository service wrote:
Author: jakllsch
Date: Sun May 22 17:39:25 2011
New Revision: 6608
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6608
Log
On 5/22/11 1:07 PM, Jonathan A. Kollasch wrote:
On Sun, May 22, 2011 at 12:28:41PM -0700, Stefan Reinauer wrote:
On 5/22/11 8:12 AM, Jonathan A. Kollasch wrote:
Optionally treat ck804 memory-mapped PCI configuration space window as a
resource. Not enabled by default because the resource
Did you check the output file? In my tests a .align 4 aligned to 4 bytes not
16.
Sent from my mobile phone
On 22.05.2011, at 19:18, "Scott Duplichan" wrote:
> Stefan Reinauer wrote:
>
> ]>>> +.align 4
> ]>> Shouldn't this be .align 16 then?
>
* Jonathan A. Kollasch [110523 12:52]:
> On Sun, May 22, 2011 at 12:25:37PM -0700, Stefan Reinauer wrote:
> > On 5/22/11 8:39 AM, repository service wrote:
> > >Author: jakllsch
> > >Date: Sun May 22 17:39:25 2011
> > >New Revision: 6608
> > >UR
* Jonathan A. Kollasch [110523 21:28]:
> Add ACPI automatic PIC/APIC interrupt routing logic for ck804.
>
> Signed-off-by: Jonathan Kollasch
> Index: src/southbridge/nvidia/ck804/acpi/ck804.asl
> ===
> --- src/southbridge/nvidia/ck
* shawn Bai [110522 06:28]:
>
> Hi,folks,
> I searched for 'acpi_tables.c' in directory 'mainboard', and 49
> entries come.They are as follows, but not all listed here,just for
> your reference.
[..]
> I don't know ACPI and don't know the reason why there are so many
> files with the same name
On 5/29/11 4:44 PM, Raleigh Boulware wrote:
Is there a good link to this tool chain?
There are no prebuilt binaries for this tool chain. Type 'make crossgcc'
in coreboot, as suggested several times before in this thread;-)
Stefan
> Date: Sun, 29 May 2011 20:05:47 +0300
> From: cristi.maghe
On 5/29/11 6:06 PM, Gregg Levine wrote:
Hello!
Group I returned from vacation, (which is where SVN worked) on the
Friday. Today I went ahead and attempted the regular and routine
update of SVN. Stefan is it possible, however unlikely that something
where you are located happens to be blocking any
* Joe Holden [110601 22:29]:
> Hi guys,
>
> Not sure if this is the right place to ask, but what are the chances
> of the above board being supported?
>
> I have a couple in use and they look like pretty standard ICH7/945
> boards: http://www.mini-itx.com/store/?c=47#jnc92-330
Slight modificati
On 6/1/11 10:52 PM, Thomas Rohloff wrote:
Hi,
I have a AsRock 870 Etreme3
( http://www.asrock.com/mb/overview.asp?model=870%20extreme3 ) and
wanted to know if it's supported b coreboot.
See http://www.coreboot.org/Supported_Motherboards for a list of
supported boards.
So, is this possible?
* Jonathan A. Kollasch [110525 18:59]:
> > > + If (LEqual (Arg0, 8)) {
> > white spaces look messed up
>
> No, that was intentional, i wanted the LEqual to line up,
> though then I didn't pad the single character numbers ...
Sorry not sure what you were trying to achieve. As long as the co
* Thomas Rohloff [110603 12:33]:
> Am Thu, 02 Jun 2011 06:37:16 -0700
> schrieb Stefan Reinauer :
>
> > On 6/1/11 10:52 PM, Thomas Rohloff wrote:
> > > Hi,
> > > I have a AsRock 870 Etreme3
> > > ( http://www.asrock.com/mb/overview.asp?model=870%20e
* repository service [110604 17:44]:
> Author: stuge
> Date: Sat Jun 4 17:44:31 2011
> New Revision: 6625
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6625
>
> Modified: trunk/src/mainboard/asrock/e350m1/romstage.c
>
* repository service [110604 17:44]:
> Author: stuge
> Date: Sat Jun 4 17:44:54 2011
> New Revision: 6626
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6626
>
> Log:
> Port persimmon r6583 to e350m1: pstate 0 early
>
> Switch processor cores to pstate 0 early to reduce boot time.
* repository service [110604 17:45]:
> Author: stuge
> Date: Sat Jun 4 17:45:12 2011
> New Revision: 6627
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6627
>
> Log:
> Port persimmon r6584 and r6601 to e350m1: SPI prefetch early
>
> Enable SPI cacheline prefetch early to reduce bo
* repository service [110604 17:47]:
> Author: stuge
> Date: Sat Jun 4 17:47:05 2011
> New Revision: 6633
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6633
>
> Log:
> Port persimmon r6591 to e350m1: ROM cache early
>
> Enable rom cache early to reduce boot time.
>
> Signed-off-b
* Peter Stuge [110604 18:16]:
> Stefan Reinauer wrote:
> > > +++ trunk/src/mainboard/asrock/e350m1/romstage.c Sat Jun 4 17:44:31
> > > 2011(r6625)
> ..
> > > +__outdword (0xcf8, 0x8000a3a0);
> >
> > what's the reason to not use p
* Peter Stuge [110604 18:19]:
> Stefan Reinauer wrote:
> > > +++ trunk/src/mainboard/asrock/e350m1/romstage.c Sat Jun 4 17:45:12
> > > 2011(r6627)
> > > @@ -50,6 +50,13 @@
> > >// all cores: set pstate 0 (1600 MHz) early to save a few ms
On 6/4/11 3:22 PM, dove - railing wrote:
I am not a techie.
Would it be correct to say that fonts at the Bios level are decided by
the Video card / VGA firmware?
The VGA BIOS loads the initial font.
Is there an opensource utility for them?
I found this, it's not open source though:
http:/
On 6/4/11 10:47 AM, Sven Schnelle wrote:
motherboards can use this hook to get notified if someone writes
to the APM_CNT port (0xb2). If the hook returns 1, the chipset
specific hook is also skipped.
Signed-off-by: Sven Schnelle
Acked-by: Stefan Reinauer
---
src/include/cpu/x86/smm.h
there are no event queue registers in the EC register space,
we're using 0x62/0x66 as EC I/O ports as long as ACPI is disabled.
Signed-off-by: Sven Schnelle
Acked-by: Stefan Reinauer
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
* dove - railing [110619 14:11]:
> I have phoned Australia and spoke to an expert in Procon.com.au about 2 times
> and corresponded via email. Procon.com.au are wanting several hundred dollars
> whether it's my font or theirs. This is not affordable. I don't know why
> vga
> bios is proprieta
Hi Darren,
* Darren Hart [110621 00:19]:
> I'm new to coreboot and just trying to get it to boot into qemu. I've
> tried using SeaBios as well as just copying "yes" to payload.elf. I
> updated the Makefile to use gcc 4.5 instead of the 4.4 that ships with
> my distribution (Ubuntu 10.10):
> Ind
On Tue, Jun 21, 2011 at 8:34 PM, Kevin O'Connor wrote:
>
> On Mon, Jun 20, 2011 at 10:58:06PM -0700, Darren Hart wrote:
> > On 06/20/2011 04:09 PM, Cristian Măgherușan-Stanciu wrote:
> > > Hi,
> > >
> > > I documented the latest developments (git and crossgcc) at
> > > http://www.coreboot.org/Buil
On 7/2/11 2:08 PM, Rudolf Marek wrote:
Hi,
Yes even 486 would be good fit! (It has more closer aligns etc). As
Stefan mentioned, some CPU might not have SSE enabled failing to
execute coreboot. Maybe this is a bit broader problem.
Thanks
Rudolf
Note that this problem does not happen with th
* Hamo [110726 11:05]:
> Hi lists,
> As I have moved forward to writing the ramstage, much more problems came out.
> PCI devices are just extra devices that can be used but not key
> devices like those on X86. Most devices on ARM are connected through
> AHBA bus and can be configured by reading an
On 8/1/11 1:28 PM, Marc Jones wrote:
Tadas,
On Mon, Aug 1, 2011 at 1:08 PM, Tadas Slotkus wrote:
Hi, thank you both for the answers. I have studied libpci from
libpayload and removed that device list generation with mallocs. Done a
bunch of trial-error cleanup and now chipset enable and probi
* Tadas Slotkus [110811 00:32]:
>
> > There will be a problem leaving the XIP area cached while trying to
> > write to the flash. At the least this means it's not possible to write
> > the whole flash. Is this intended? What's the plan here?
>
> Should it be possible to map flash contents in c
* Dsouza, Malcolm [110809 14:40]:
> Thanks Corey,
>
>
>
> 1. I agree that before reading through the code, it is better to first check
> if the BIOS guides are available. However I would still like the answer to
> my question if I wish to carry on with the investigation for now.
> 2.
On 8/22/11 1:37 AM, Paul Menzel wrote:
Am Montag, den 22.08.2011, 04:55 +0200 schrieb Alec Ari:
Alec Ari (neotheu...@ymail.com) just uploaded a new patch set to gerrit, which
you can find at http://review.coreboot.org/166
-gerrit
commit d402be72762f60d4b60edf5662d31a14eccb03ec
Author: Alec Ar
* Pedro Armando Ojeda May [110922 07:08]:
> I send you the information requested in the wiki of coreboot.
The chipset is supported, the laptop itself is not.
Please get it working and send a patch! :-)
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/c
On 10/10/11 9:02 AM, Alp Eren Köse wrote:
As written on the subject 'make crossgcc' fails as following:
Skipping GDB as requested by command line
Building IASL 20110623 ... failed
make[1]: *** [build-without-gdb] Error 1
make: *** [crossgcc] Error 2
Anyone knows why?
and the
"util/crossgcc/acpi
* Myles Watson [111012 08:19]:
> On Tue, Oct 11, 2011 at 10:13 PM, Oskar Enoksson wrote:
> > I get the following warnings:
> >
> > APIC: 00 missing read_resources
> > APIC: 01 missing read_resources
> > APIC: 02 missing read_resources
> > APIC: 03 missing read_resources
> > I2C: 01:08 missing rea
* Marc Jones [111014 06:22]:
> On Thu, Oct 13, 2011 at 3:19 AM, She, Kerry wrote:
> > Hello,
> >
> >
> >
> > Some mainboard support more than one family of CPUs with same socket type,
> >
> > Such as SuperMicro/h8scm:
> >
> > http://www.supermicro.com/Aplus/motherboard/Opteron4100/SR56x0/H8SCM-F.
* Marc Jones [111016 10:10]:
> >> > I have created 2 devicetree file :
> >> >
> >> > devicetree_f15.cb for platform with family 15 CPU
> >> >
> >> > devicetree_f10.cb for platform with family 10 CPU
> >> >
> >> >
> >> >
> >> > I changed the makefile to create a symbol link “devicetree.cb” link to
* Alp Eren Köse [111018 11:25]:
> Hi thanks all for your help,
>
> I have arranged the "devicetree.cb" as suggested, you can see it at the
> attachment.
> Put the superio chip under the LPC bridge section, but I didn't get how did
> you
> know it?
>
> Added those to the romstage.c:
> > #include
* Alp Eren Köse [111018 17:02]:
> By the way I do not have a "CMC state machine binary", which it says:
> #We don't ship that, but booting without it is bound to fail
> in the src/southbridge/intel/sch/Makefile.inc file. What is it, how can get
> it?
>
> Is it likely for that to cause this seria
On 10/24/11 3:15 AM, Patrick Georgi wrote:
Therefore, I propose (http://review.coreboot.org/#change,320) to get
rid of the "big bootblock" variant altogether. This might break some
boards (silently: they still build, but they fail on boot), but at
least it forces action to fix them.
Advantage
On 11/22/11 5:20 AM, Kyösti Mälkki wrote:
Hi
Could someone explain the use of boot_cpu() in bootblock_normal.c
main()? I thought only the BSP CPU executes this code (currently)?
I am about to push a change that does early SMP init for hyper-threading
CPUs to allow cache-as-ram implementation. S
On Tue, 22 Nov 2011 08:01:01 +0200, Kyösti Mälkki wrote:
On Tue, 2011-11-22 at 06:30 +0900, Stefan Reinauer wrote:
On 11/22/11 5:20 AM, Kyösti Mälkki wrote:
> Hi
>
> Could someone explain the use of boot_cpu() in bootblock_normal.c
> main()? I thought only the BSP CPU execut
On 12/31/11 5:00 AM, ali hagigat wrote:
I downloaded the coreboot version 4 for a Ubuntu system. When i want to execute
util/crossgcc/make
It stops complaining that there is an error building GDB!
If i want to make without GDB like by buildgcc, it stops , the error
is that it can not find one h
601 - 700 of 1444 matches
Mail list logo
