[coreboot] Re: Memory Down approach Error on intel Denverton board

Hi, Did you adjusted mMemoryDownConfig structure in mainboard`s romstage.c file to much your memory down configuration? Refer to commented out example just above structure definition. Also double check if .SpdDataPtr structure member for memory down slot has correct pointer to spd.bin content.

[coreboot] Re: Gerrit shows a Merge Conflict (was: Re: Denverton-NS refactoring)

... and a little note: This is only for DNV/HCV (as we are team dedicated to them). No change for other Intel hw. They are handled by other Intel teams. Mariusz -Original Message- From: Szafranski, MariuszX Sent: Wednesday, January 19, 2022 10:49 AM To: Peter Stuge ; coreboot

[coreboot] Re: Gerrit shows a Merge Conflict (was: Re: Denverton-NS refactoring)

Hi, To clarify situation (Jeff - looks like you got wrong my last email  ) DNV will still be supported by Intel. Vanessa will continue to be primary support contact from Intel side. One thing that will change in next few months is that I and Suresh will move to another project and will have

[coreboot] Re: A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

Hi Furquan, Thanks for pointing. I`ve missed this patch series. Yeah omitting the `device lapic` line from the devicetree and adding this patch looks like correct (common) way to handle this issue. BR, Mariusz > > have you tried omitting the `device lapic` line from the devicetree? > > I have

[coreboot] Re: A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

how this magic works :)! lapic 0xbeef . As it is DNV specific it is just moved to DNV subdirectory without touching coreboot core. BR, Mariusz From: Дмитрий Понаморев Sent: Friday, August 20, 2021 11:40 PM To: Szafranski, MariuszX Cc: Sumo ; Jay Talbott ; Coreboot Subject: Re: [coreboot]

[coreboot] [RFC] Intel split stack IIO design support in coreboot - new multidomain approach

Hi, RFC/initial proposal how to implement split IIO in coreboot: [RFC] Intel IIO split stack - multidomain approach (I38ac830e) * Gerrit Code Review (coreboot.org) thx for all comments, suggestions BR, Mariusz

[coreboot] Re: A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

Hi, Maybe keep 0 for apicid in devicetree.cb and add something like below to denverton soc_init (or define separate function for check and fixup) in src/soc/intel/denverton_ns/chip.c. Could anyone with apicid != 0 test and let us know? BR, Mariusz static void soc_init(void *data) { unsigned

[coreboot] Re: denverton_ns: failed to write RW_MRC_CACHE

, Sumo On Fri, Jun 11, 2021 at 9:05 AM Szafranski, MariuszX mailto:mariuszx.szafran...@intel.com>> wrote: Hi Sumo, It should be simple as adding SPI early init to bootblock. You could try to add call to fast_spi_early_init(DEFAULT_SPI_BASE); at the end of bootblock_soc_early_init functio

[coreboot] Re: denverton_ns: failed to write RW_MRC_CACHE

Hi Sumo, It should be simple as adding SPI early init to bootblock. You could try to add call to fast_spi_early_init(DEFAULT_SPI_BASE); at the end of bootblock_soc_early_init function from src/soc/intel/denverton_ns/bootblock/bootblock.c I suspect that after that MRC writing should also work in

[coreboot] Re: coreboot image forIntel Harcuvar CRB

Hi Tirumalesh, Please verify if FSP is correctly integrated. Especially if FSP-T part is enabled and used for setting up CAR. config mainboard section: vendor->Intel, model->Harcuvar, romsize ->16M, (insert your actual SPI flash size) cbfs size 8M (0x80) (or adjust for your needs) config

[coreboot] Re: Regarding Intel CPU frequency.

Hi Nitin, Look`s like SpeedStepping in action - correct behavior while on idle. Please put more stress on CPU and recheck - It should jump back to 2200 BR, Mariusz -Original Message- From: nitin.ramesh.si...@gmail.com Sent: czwartek, 23 kwietnia 2020 14:36 To: coreboot@coreboot.org

Re: [coreboot] Atom c3000 Harcuvar and Intel ME

Hi, In case of Harcuvar CRB we have 16M SPI flash: first 8M for ME (which is outside of CBFS) and last 8M for coreboot. We need to specify two things in coreboot config: - ROM chip size – 16M – physical size of SPI flash (needed for correct flash offset calculations inside coreboot

Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works

.. from git repo at https://github.com/tianocore/edk2 (master branch) From: Melissa Yi [mailto:hu...@celestica.com] Sent: Friday, September 22, 2017 10:53 AM To: Szafranski, MariuszX <mariuszx.szafran...@intel.com> Cc: coreboot@coreboot.org Subject: Re: [coreboot] 64 UEFI payload boot

Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works

Hi, It was tested on Denverton_NS platform using mainly 64bit UEFI payload. 32bit UEFI payload was tested also. Both UEFI payload versions should behave similarly when built from same source code using same coreboot configs. I didn`t noticed difference between 32 and 64 versions. BR, Mariusz