[coreboot] AMD IMC open source firmware replacement

Hello, you can try with: lspci -vvv -- Vincent Legoll -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] INT 13, real mode, block write commands and coreboot

an site & forum, see [1] > Important is that the SBC support UBUNTU / UBUNTU-like > O.S. There is an ubuntu flavored armbian, have a look there: [1] https://www.armbian.com/ -- Vincent Legoll -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] INT 13, real mode, block write commands and coreboot

surface, if you're after someone who knows his thing, you'll have to eventually go deeper, as some disk firmwares have already been modified to hide some data even from the OS. -- Vincent Legoll -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] INT 13, real mode, block write commands and coreboot

from threre for other interfaces like SATA... -- Vincent Legoll -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Dell PE2850 with coreboot.

(to another host) setup and working is good to have, because VGA may not work at first. -- Vincent Legoll -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] How Coreboot can help in malware reverse engineering ?

that this makes sense in the context... -- Vincent Legoll -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] simple useful utility

On Sat, Oct 11, 2008 at 11:45 PM, ron minnich [EMAIL PROTECTED] wrote: On Sat, Oct 11, 2008 at 1:51 PM, Vincent Legoll [EMAIL PROTECTED] wrote: On Sat, Oct 11, 2008 at 10:31 PM, ron minnich [EMAIL PROTECTED] wrote: That is really nice. Yes, now we just need it for config and io and prefmem

Re: [coreboot] simple useful utility

unspecified bits of the limit are assumed to be 1s. [...] For the limit registers I assumed the unspecified bits are 0-24, and I set them to 0xFF. Is that the right thing to do ? Idem for base registers, with 24 bits set to 0x00 ? -- Vincent Legoll -- coreboot mailing list: coreboot

Re: [coreboot] simple useful utility

to test on. But after a quick glance, it all looks the same, so it should work as-is. I'd also like comments, and any ideas for further improvements. If this is useful, it is: Signed-off-by: Vincent Legoll [EMAIL PROTECTED] and could go somewhere in the utils directory... -- Vincent Legoll

Re: [coreboot] [PATCH] v3: VIA C7 CAR

and report that fact (post code, beep code, serial console printk) ? Knowing that it's the CPU that is broken would allow one not to throw away the other good parts of the computer... -- Vincent Legoll -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] simple useful utility

Interleave select: 0b111 DRAM Limit: 0x00EFFF -- Vincent Legoll -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] ECS AMD690GM-M2 AM2 AMD 690G Micro ATX AMD Motherboard

to buy one. Are there any cheap ones out there ? -- Vincent Legoll -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] simple useful utility

On Sat, Oct 11, 2008 at 2:52 AM, ron minnich [EMAIL PROTECTED] wrote: On Fri, Oct 10, 2008 at 5:06 PM, Vincent Legoll [EMAIL PROTECTED] wrote: Is that like what you had in mind: This is 18:1 right? yes ~ # ./AMDK8MemMap.py 0x00: Ox1022 - Device ID 0x02: Ox1101 - Vendor ID 0x04

Re: [coreboot] simple useful utility

and MSRs. I would be curious to read your code. -- Vincent Legoll -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] simple useful utility

the python prototype before starting to work on a C version, though... -- Vincent Legoll -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] simple useful utility

registers I wrote one of these for the ultra 40 project and then lost it when I shipped the machine back to xtreme data ... it's easy but I don't have time today. It might tell us what is up with v3/serengeti. I might give that a shot if it's not too difficult -- Vincent Legoll -- coreboot

Re: [coreboot] simple useful utility

Address -- Vincent Legoll -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] simple useful utility

00 00 00 00 00 00 00 00 b0: 03 0a 00 00 00 0b 00 00 03 00 80 00 00 d3 fe 00 c0: 00 00 00 00 00 00 00 00 13 10 00 00 00 f0 0f 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- Vincent

Re: [coreboot] corebootV2 Can support IEI lx-800 mainboard?

recommend 3. One is a copy of factory bios. Because, every once in a while, I accidentally flash the factory bios with a broken coreboot. Having a backup for the backup is very useful. I can only second that, as it happened to me too. -- Vincent Legoll -- coreboot mailing list: coreboot

Re: [coreboot] Intel i855pm northbridge

... Thanks for the i3100 hint, btw -- Vincent Legoll -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Intel i855pm northbridge

enlighten me ? -- Vincent Legoll -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] patch: all superios in v3 are set up wrong

On Fri, Oct 3, 2008 at 6:54 PM, Uwe Hermann [EMAIL PROTECTED] wrote: + kbirq = 1; + kbirq2 = 12; And this should probably be 2, not 12. if kbirq2 is for the second ps2 port, i.e. ps2 mouse, maybe irq 12 is right. -- Vincent Legoll -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] r3622 - in trunk/coreboot-v2: src/mainboard/asus/a8n_e targets/asus/a8n_e

[i] = hcdnx[i]; Looks like a cut'n'paste error or a mismerge. Or is there something magical behind that variable that really needs to be written 2 times in a row ? If this is the case I would add a big fat comment about that fact... -- Vincent Legoll -- coreboot mailing list: coreboot

Re: [coreboot] Tyan S2892 lspci

model to cope in a kludgy way, though. The HT graph that is on NUMA opterons dual and quad setups would be a problem too, I think. -- Vincent Legoll -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Please list soldered/non-soldered BIOS

in the status column for some motherboards, and sometimes the best email adress you should use for that kind of questions is the ML... I'm looking forward to use coreboot so thank you for bringin up this fine piece of software to the community. Idem -- Vincent Legoll -- coreboot mailing list

Re: [coreboot] GA-M57SLI-S4 is AMD Phenom x4 compatible

. -- Vincent Legoll -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Opteron 165 in v2

On Wed, Sep 10, 2008 at 7:04 PM, Peter Stuge [EMAIL PROTECTED] wrote: Vincent Legoll wrote: is there something to be careful about, when using opteron 165 (dual core opteron without registered ECC ram support) Not that I know of, but maybe someone else knows. Has anyone run coreboot

Re: [coreboot] Opteron 165 in v2

? eventually with debug apic=debug loglevel=9 parameters a coreboot log. Again, thanks -- Vincent Legoll -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Kernel hang solid

=debug output is now the same for coreboot-based or BIOS-based boots. Where could I have more infos on other IRQs not listed there (for example the IRQs 3 4 that are being used for serial port when booted with legacy bios). Kernel is silent about them at that stage of the boot process. -- Vincent

Re: [coreboot] wiki account request (for GRUB 2)

, then. -- Vincent Legoll -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Kernel hang solid

On Fri, Sep 5, 2008 at 11:38 AM, Vincent Legoll [EMAIL PROTECTED] wrote: On Fri, Sep 5, 2008 at 5:03 AM, yhlu [EMAIL PROTECTED] wrote: does previous kernel work? like 2.6.24 I've not tried a kernel that old, but I will. I've tried vanilla -git for last few days only. Tested 2.6.{23,24,25

Re: [coreboot] Kernel hang solid

On Fri, Sep 5, 2008 at 10:21 PM, Vincent Legoll [EMAIL PROTECTED] wrote: Tested 2.6.{23,24,25} they all hang the same way at the same place: the first console_initcall() (which I don't know if it is the serial one or the vga one) I've narrowed it to the down(console_sem) in acquire_console_sem

[coreboot] Added Shuttle SN25P wiki page links

Hello, While I still have that info fresh in my head, I wrote what I did for the Shuttle SN25P mainboard port. main page: http://www.coreboot.org/Shuttle_SN25P linked from entry in supported mainboards Thanks to all who helped me getting there, I hope collaboration will continue. -- Vincent

Re: [coreboot] Added Shuttle SN25P wiki page links

On Thu, Sep 4, 2008 at 4:11 PM, Peter Stuge [EMAIL PROTECTED] wrote: Vincent Legoll wrote: http://www.coreboot.org/Shuttle_SN25P Great notes! Only comment I can think of is to keep the tested kernel options around even if they are discarded as not being useful, to keep record of what has

Re: [coreboot] Added Shuttle SN25P wiki page links

, but still...) What would be cool, is an option in the coreboot build process to use the ACPI tools to extract tables from the running legacy BIOS and stuff them in the image being built. But would that be technically possible ? -- Vincent Legoll -- coreboot mailing list coreboot@coreboot.org http

[coreboot] Kernel hang solid

, the hang happen at init/main.c in console_init() -- Vincent Legoll Linux version 2.6.27-rc5-00100-gec0c15a ([EMAIL PROTECTED]) (gcc version 4.3.1 (Gentoo 4.3.1-r1 p1.1) ) #19 SMP Wed Sep 3 21:11:57 CEST 2008 Command line: apic=debug debug kgdbwait irqpoll loglevel=8 earlycon=uart8250,io,0x3f8,115200n8

[coreboot] New trunk/filo branch

to mess with MAKEFLAGS that way, so I removed it and used plain shell variables. I removed the duplicated -m32 too. -- Vincent Legoll build-sh-fix.patch Description: Binary data -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Wiki account

On Sun, Aug 31, 2008 at 6:36 PM, Peter Stuge [EMAIL PROTECTED] wrote: Vincent Legoll wrote: And I found why it was failing for me: all the $(CC) calls made in Makefile are not -m32-ized, especially the -print-libgcc-file-name one... So why not just CC=$(CC) -m32 Yes, that's a smaller

Re: [coreboot] Wiki account

On Sun, Aug 31, 2008 at 6:40 PM, Vincent Legoll [EMAIL PROTECTED] wrote: So why not just CC=$(CC) -m32 Yes, that's a smaller (better) equivalent patch Here is what I came with, implementing Peter's idea -- Vincent Legoll add-missing-m32.patch Description: Binary data -- coreboot mailing

[coreboot] build.sh

\ NM=i386-elf-nm \ HOSTCC=gcc \ - -j + -j \ fi if [ $OS == Linux ]; then -- Vincent Legoll build-sh-fix.patch Description: Binary data -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] build.sh

The remaining failure is : [...] make: invalid option -- '3' make: invalid option -- '2' make: invalid option -- '' Usage: make [options] [target] ... [...] this is the make $MAKEFLAGS line make-3.8 bash-3.2.39 any idea -- Vincent Legoll -- coreboot mailing list coreboot@coreboot.org http