[coreboot] BIOS Flashing

Is there a coreboot BIOS flash available for an unknown motherboard in a customized PC? The motherboard is more than 10 years old. If there is a coreboot BIOS flash for it, will it add secure boot and TPM 2.0? -- Disclaimer The information contained in this communication from the sender is

[coreboot] [Part 2] Dell OptiPlex and coreboot BIOS - a story about porting cursed hardware

Great news: we at 3mdeb have advanced in porting Dell Optiplex 7010⁄9010 to coreboot! And, if you would like to see what it takes to add coreboot support for the cursed hardware - from a coreboot developer's point of view! - here's a new highly entertaining blog post by Michal Zygowski: https://blo

[coreboot] Re: Coreboot BIOS question

Hello Aaron, That error message appears to be coming from Pfsense. After searching around a bit, it appears that the boot loop issue has occurred in multiple models of Pfsense firewall appliances and is due to filesystem corruption. The most common suggestion I see is to reboot into single user mod

[coreboot] Coreboot BIOS question

Hello, I am a new user of Coreboot who recently purchased a Protectli firewall with Coreboot pre-installed. The firewall is running PfSense that I installed on it. Everything was going ok for a few days until I started having issues with PfSense and now I am having problems getting PfSense to l

[coreboot] Bios Corrupted

Hello sir , I need a little bit help I accidentally corrupted bios of my laptop during bios update ...before it blackout... i saw the txt .." searching for bios firmware ... bios firmware not found " I baught a ch341A usb bios programming device ... I think a .bin file may bring my laptop back

[coreboot] Bios problem. Will not boot

Hi everyone, I have a problem. I had flashed my bios last year into coreboot by a raspberry pi. Now, I changed the hard disk of that laptop, and put another one with windows on it, but it does not boot there. Every key that I press it gets me to booting from hard disk, and again the process repea

[coreboot] BIOS chip address range?

Hi, If I theoretically had a flash chip that was larger than 128Mb, it requires 3-4 byte addressing. Does / could coreboot support such large memory, or would the limitation live somewhere else in the system? Cheers, R ___ coreboot mailing list -- coreb

Re: [coreboot] BIOS upgrade before flashing coreboot

Am 07.06.2018 18:46 schrieb Merlin Büge: On Thu, 7 Jun 2018 12:05:34 +0200 Akendo wrote: Hey everyone, currently I working on a x220 to flash coreboot onto it. I notice that my x220 has a current BIOS version from 2011 (1.24 UEFI/BIOS and 1.13 ECP). Within the change-log[0] variates updates

Re: [coreboot] BIOS upgrade before flashing coreboot

On Thu, 7 Jun 2018 12:05:34 +0200 Akendo wrote: > Hey everyone, > > currently I working on a x220 to flash coreboot onto it. I notice that > my x220 has a current BIOS version from 2011 (1.24 UEFI/BIOS and > 1.13 ECP). > > Within the change-log[0] variates updates and fixes are stated. > Inc

[coreboot] BIOS upgrade before flashing coreboot

Hey everyone, currently I working on a x220 to flash coreboot onto it. I notice that my x220 has a current BIOS version from 2011 (1.24 UEFI/BIOS and 1.13 ECP). Within the change-log[0] variates updates and fixes are stated. Including changes to the ME engine. Within many documentation part of c

Re: [coreboot] BIOS/CoreBoot/UBOOT

taii...@gmx.com wrote: > >>> 3. Support for Secure Boot - would one approach be simpler than another? > >> SB was invented by MS for DRM, it serves no real security purpose IMO > > > > I'd like to ask you to reconsider that opinion. > > It is a fact not an opinion. You wrote "IMO", otherwise I p

Re: [coreboot] BIOS/CoreBoot/UBOOT

Hello Taiidan, taii...@gmx.com: > On 04/12/2018 11:43 AM, Peter Stuge wrote: >> taii...@gmx.com wrote: 3. Support for Secure Boot - would one approach be simpler than another? >>> SB was invented by MS for DRM, it serves no real security purpose IMO >> I'd like to ask you to reconsider that

Re: [coreboot] BIOS/CoreBoot/UBOOT

On 04/12/2018 11:43 AM, Peter Stuge wrote: > taii...@gmx.com wrote: >>> 3. Support for Secure Boot - would one approach be simpler than another? >> SB was invented by MS for DRM, it serves no real security purpose IMO > I'd like to ask you to reconsider that opinion. > It is a fact not an opinion.

Re: [coreboot] BIOS/CoreBoot/UBOOT

On Thu, Apr 12, 2018 at 2:18 PM, wrote: > > - Mail d'origine - > De: Peter Stuge > À: coreboot@coreboot.org > Envoyé: Thu, 12 Apr 2018 17:43:48 +0200 (CEST) > Objet: Re: [coreboot] BIOS/CoreBoot/UBOOT > > ... > > Most people who buy computers are happ

Re: [coreboot] BIOS/CoreBoot/UBOOT

> Is it possible to go from BIOS/UEFI to UBOOT (on-board)? How? Actually, since you are using, after all, YOCTO Project to build your BDX-DE BSP, you can freely use U-Boot, if Bin Meng (U-Boot BSP maintainer) already integrated BDX-DE/Camelback CRB's FSP into U-Boot. If? Bin, Did you integrate

Re: [coreboot] BIOS/CoreBoot/UBOOT

Hi, On 11 April 2018 at 16:39, Raymond Yeung wrote: > > I currently have a board that uses Intel Xeon D (previously codenamed > Broadwell DE). It boots up with BIOS/UEFI. I 'm exploring other oot-up > options here. > > > I'm not familiar with this early stage of system initialization. It seem

Re: [coreboot] BIOS/CoreBoot/UBOOT

taii...@gmx.com wrote: > > 3. Support for Secure Boot - would one approach be simpler than another? > > SB was invented by MS for DRM, it serves no real security purpose IMO I'd like to ask you to reconsider that opinion. Secure Boot is mandated by Microsoft to provide Microsoft and Microsoft's

Re: [coreboot] BIOS/CoreBoot/UBOOT

At this point, on this platform, I think your fastest bet to mostly open sourcing it all is linuxboot. We recently had an experience where we installed a linux kernel in FLASH on two new boards in two days and most of that was just figuring out how to rearrange the UEFI bits, (i.e. move the furnit

Re: [coreboot] BIOS/CoreBoot/UBOOT

nfirm.  UEFI seems > to already have this aspect covered. > > > Raymond > > > > > *From:* David Hendricks > *Sent:* Wednesday, April 11, 2018 6:03 PM > *To:* Raymond Yeung > *Cc:* coreboot@co

Re: [coreboot] BIOS/CoreBoot/UBOOT

On 04/11/2018 09:54 PM, Raymond Yeung wrote: > Thanks David for the detailed response. > > > My main motivation to go down Coreboot/UBOOT route is to attempt to simplify > the remaining boot-up to Linux. Instead of using PXE-BOOT, we could use tftp > only. Am I correct to say that? If you want

Re: [coreboot] BIOS/CoreBoot/UBOOT

2018 6:03 PM To: Raymond Yeung Cc: coreboot@coreboot.org Subject: Re: [coreboot] BIOS/CoreBoot/UBOOT On Wed, Apr 11, 2018 at 3:39 PM, Raymond Yeung mailto:rksye...@hotmail.com>> wrote: I currently have a board that uses Intel Xeon D (previously codenamed Broadwell DE). It boots up with BIOS

Re: [coreboot] BIOS/CoreBoot/UBOOT

On 04/11/2018 06:39 PM, Raymond Yeung wrote: > I currently have a board that uses Intel Xeon D (previously codenamed > Broadwell DE). It boots up with BIOS/UEFI. I 'm exploring other oot-up > options here. Let us know what you are attempting to accomplish. > I'm not familiar with this early sta

Re: [coreboot] BIOS/CoreBoot/UBOOT

On Wed, Apr 11, 2018 at 3:39 PM, Raymond Yeung wrote: > I currently have a board that uses Intel Xeon D (previously codenamed > Broadwell DE). It boots up with BIOS/UEFI. I 'm exploring other oot-up > options here. > > > I'm not familiar with this early stage of system initialization. It seems

[coreboot] BIOS/CoreBoot/UBOOT

I currently have a board that uses Intel Xeon D (previously codenamed Broadwell DE). It boots up with BIOS/UEFI. I 'm exploring other oot-up options here. I'm not familiar with this early stage of system initialization. It seems BIOS/UEFI to Linux needs to use PXE, with the need to configure

Re: [coreboot] Coreboot Bios Compatibility

I'll also repeat the advice I always give: BEFORE you start a new, untested mainboard, follow the entire process of creating coreboot for a known good mainboard. You'll probably make all the mistakes I still make, and it's much easier to work on a tested mainboard first. This is not like installin

Re: [coreboot] Coreboot Bios Compatibility

On Sun, December 3, 2017 2:14 pm, Raziel in Shambles wrote: > i'd like to know if it is possible to flash the coreboot bios to my mobo. > https://www.gigabyte.com/Motherboard/GA-MA790GP-DS4H-rev-10#sp Check these to see if there is already support for your motherboard: https://www.c

Re: [coreboot] Coreboot Bios Compatibility

OS overclocking tools such as turionpowercontrol for AMD CPUs which works under Linux. Also, https://www.coreboot.org/Build_HOWTO Best regards , Ivan Ivanov 2017-12-03 17:14 GMT+03:00 Raziel in Shambles : > Hello, > > > i'd like to know if it is possible to flash the coreboot bi

[coreboot] Coreboot Bios Compatibility

Hello, i'd like to know if it is possible to flash the coreboot bios to my mobo. If so might i also burden you for a brief tutorial, aside from the one provided on coreboot.org, on how to actually build this bios (f.e. does it need to be i386 or x64, howto configure the payload,

Re: [coreboot] BIOS log in coreboot

Hi Vincenzo, I had the same issue just a day ago and solved it with cbmem When building coreboot, make sure you have selected the "Send console output to a CBMEM buffer"-option (Run `make menuconfig` and select `Console`) and then use the `cbmem` tool (in `util/cbmem` in the coreboot git repo) Ha

Re: [coreboot] BIOS log in coreboot

On Wed, Nov 22, 2017 at 10:09 AM, ingegneriafore...@alice.it < ingegneriafore...@alice.it> wrote: > Hello Guys ! > > I apologize with you if my question seems silly: > > can you tell me if Coreboot stores a log of the POST phase in its EPROM > memory ? > > If so, is it possible to retrive the log

[coreboot] BIOS log in coreboot

Normal 0 14 false false false IT X-NONE X-NONE MicrosoftInternetExplorer4 Hello Guys ! I apologize with you if my question seems silly: can you tell me if

[coreboot] BIOS region alignment on ivybridge platforms.

Hi Nicola Corna and Marek Behun, I have reported that a coreboot image with a cleansed and truncated ME region may cause the first boot costing more than 5 minutes (https://mail.coreboot.org/pipermail/coreboot/2017-April/084004.html). Now I confirm that in order to prevent this, the bios region sh

[coreboot] BIOS for Biostar AM1ML not working

Yesterday I tried to build my first coreboot BIOS and everything went fine. I followed the instructions and flashed the mainboard (using flashrom) with the built rom. Unfortunately, the mainboard is dead now. Fan starts spinning when I turn the computer on, but screen stays black. Is there any

Re: [coreboot] bios for ATOM E38XX

Sorry, I forgot to include the contents of the ROM image: ricardo@ricardo-VirtualBox:~/BAY_TRAIL_FSP_KIT/coreboot$ build/cbfstool build/coreboot.rom print coreboot.rom: 8192 kB, bootblocksize 1024, romsize 8388608, offset 0x60 alignment: 64 bytes Name Offset Type

Re: [coreboot] bios for ATOM E38XX

Hi. I'm also trying to use Coreboot with a COM Express Module from Cogatec. It is a Conga-MA3 model [http://www.congatec.com/products/com-express-type10/conga-ma3.html]. Booting the original BIOS into Linux, and doing a cat /proc/cpu shows the processor stepping is 3, so i'm assuming it's a B3 sili

Re: [coreboot] bios for ATOM E38XX

On Wed, Jun 25, 2014 at 4:11 AM, benjamin nakache wrote: > Hello , > > > > When will support the new Atom E38XX > > > Would you or someone from your company like to help? > > > Note: This message and any attachment hereto is intended solely for the > use of the designated recipient(s) and th

[coreboot] bios for ATOM E38XX

Hello , When will support the new Atom E38XX Best Regards, Benjamin Nakache Vice President Sales cid:image001.jpg@01CE5FDD.80FF28E0 Note: This message and any attachment hereto is intended solely for the use of the designated recipient(s) and their appointed delegates

[coreboot] BIOS vendors and Linux testing (was: Feedback On Coreboot: the Solution to the Secure Boot Fiasco)

Am Mittwoch, den 02.01.2013, 10:04 -0800 schrieb ron minnich: > On Wed, Jan 2, 2013 at 9:58 AM, Andrew Goodbody wrote: > > > I am sure that it is the old story, most testing will be done against > > Windows. Anything more will be the exception. This is where the pressure > > needs to be put on th

Re: [coreboot] BIOS Savior (RD1-PMC4/8X) unavailable? Build my own?

e - >> From: "Milo Hoffmann" >> To: coreboot@coreboot.org >> Sent: Thursday, November 8, 2012 11:29:41 PM >> Subject: [coreboot] BIOS Savior (RD1-PMC4/8X) unavailable? Build my own? >> >> Hello list, >> >> I might be missing something here, b

Re: [coreboot] BIOS Savior (RD1-PMC4/8X) unavailable? Build my own?

On 09/11/12 06:29, Milo Hoffmann wrote: The datasheet does not include the /CE pin from the quick and dirty explanation. I interpret it to mean the WE# (Write Enable) pin but am seeking confirmation from more informed folks. Can anyone on the list confirm I could hook up two identical SST49LF004

Re: [coreboot] BIOS Savior (RD1-PMC4/8X) unavailable? Build my own?

Milo, My comments are inline below. dave - Original Message - > From: "Milo Hoffmann" > To: coreboot@coreboot.org > Sent: Thursday, November 8, 2012 11:29:41 PM > Subject: [coreboot] BIOS Savior (RD1-PMC4/8X) unavailable? Build my own? > > Hello list, >

[coreboot] bios chip

Hello,everyone! I'm tired to remove bios chip LPC from motherboard for flashing updated firmware coreboot all time and I broke bios socket twice. Is there any flash device I can use instead of bios chip and flash it from other host directly? -- coreboot mailing list: coreboot@coreboot.org http://w

Re: [coreboot] BIOS Disassembly Ninjutsu PDF (part of giving back to the community)

On Sat, 17 Mar 2012 23:36:08 +0700 Darmawan Salihun wrote: > I'm sorry if this is not really related to Coreboot. > I have yet to make active contribution to the project. > I have released the PDF version of my BIOS Disassembly Ninjutsu book. > Direct link: > hxxp://www.4shared.com/office/k6ooEa

[coreboot] BIOS Disassembly Ninjutsu PDF (part of giving back to the community)

I'm sorry if this is not really related to Coreboot. I have yet to make active contribution to the project. I have released the PDF version of my BIOS Disassembly Ninjutsu book. Direct link: hxxp://www.4shared.com/office/k6ooEak2/BIOS_Disassembly_Ninjutsu_Unco.html two errata have been found so f

Re: [coreboot] [PATCH v3 1/1] libpayload: add support for finding and parsing Coreboot BIOS tables

Am 23.08.2011 07:53 schrieb Philip Prindeville: > On 8/22/11 4:00 PM, Andres Salomon wrote: > >> Also, if you email the patch inline (rather than as an attachment), >> then we can include comments inline as well. >> > I wish I could, but alas I use Thunderbird. Some misguided hacker rewrot

Re: [coreboot] [PATCH v3 1/1] libpayload: add support for finding and parsing Coreboot BIOS tables

ll the kernel >> developers about the value of this patch to our users. >> >> > > I'd second this. I'm minimally familiar with coreboot, but I have no > idea what the purpose behind coreboot BIOS tables are. It allows me to identify the manufacturer and b

Re: [coreboot] Fwd: [PATCH v3 1/1] libpayload: add support for finding and parsing Coreboot BIOS tables

On 8/22/11 3:01 PM, Andrew Morton wrote: > On Sun, 21 Aug 2011 17:01:28 -0700 > Philip Prindeville wrote: > >> Attached. > > oookay. I'll await a formal patch with all the cc's, etc. > > As for the "upstream" version: if/when this patch is merged, it *is* > the upstream version. The coreboot

Re: [coreboot] [PATCH v3 1/1] libpayload: add support for finding and parsing Coreboot BIOS tables

ue of this patch to our users. > > I'd second this. I'm minimally familiar with coreboot, but I have no idea what the purpose behind coreboot BIOS tables are. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Fwd: [PATCH v3 1/1] libpayload: add support for finding and parsing Coreboot BIOS tables

On Sun, 21 Aug 2011 17:01:28 -0700 Philip Prindeville wrote: > Attached. oookay. I'll await a formal patch with all the cc's, etc. As for the "upstream" version: if/when this patch is merged, it *is* the upstream version. The coreboot tree will need to drop the old version and migrate to the

[coreboot] Fwd: Re: Fwd: [PATCH v2 1/1] libpayload: add support for finding and parsing Coreboot BIOS tables

1/1] libpayload: add support for finding and parsing Coreboot BIOS tables Date: Fri, 19 Aug 2011 16:23:27 -0700 From: Andrew Morton To: Philip Prindeville On Thu, 18 Aug 2011 20:55:56 -0700 Philip Prindeville wrote: > Hi Andrew, > > Any chance this could make it in for 3.2? Perhaps. B

Re: [coreboot] BIOS Protection Guidelines from NIST

Am Dienstag, den 17.05.2011, 12:59 +0400 schrieb Антон Кочков: > April 2011: > > http://csrc.nist.gov/publications/nistpubs/800-147/NIST-SP800-147-April2011.pdf Thank you for the URL. coreboot is not even mentioned. Searching for »source« or »closed« did not turn anything up either, so I guess h

[coreboot] BIOS Protection Guidelines from NIST

April 2011: http://csrc.nist.gov/publications/nistpubs/800-147/NIST-SP800-147-April2011.pdf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [flashrom] Need assistance for using non-coreboot bios image

2011/4/20 David Bein : > Hello Idwer, Hello David, > >  Thank you very much for the assistance. I assume > that something like: nvramtool -c 0 will force the > newly booted bios to re-compute the checksum on the cmos? I assume you want to save the current contents with "nvramtool -b cmos_content

Re: [coreboot] BIOS Saviour

Alexandr Frolov wrote: > BIOS Saviour device .. > In my board I have SST49LF080A 8 Mbit, should I use IOSS RD1-LPC8 > which is 8 MBit also? Yes. > The exerimental flash chip is still have to be unplugged to be > reprogrammed by flash programmer. This makes sense to me only if > in-circuit reprog

[coreboot] BIOS Saviour

Hello all, I am wondering about using the BIOS Saviour device (IOSS RD1). If I understood it correctly the 'original' flash card is at the bottom and 'experimental' one is at the top. The 'original' comes with IOSS RD1 kit attached to the PLCC socket and could not be removed. The experiment

Re: [coreboot] Building coreboot BIOS on a Windows computer

-Original Message- From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On Behalf Of Marc Jones Sent: Monday, August 30, 2010 10:02 AM To: Scott Cc: coreboot@coreboot.org Subject: Re: [coreboot] Building coreboot BIOS on a Windows computer On Wed, Aug 25, 2010 at 10

Re: [coreboot] Building coreboot BIOS on a Windows computer

On Wed, Aug 25, 2010 at 10:44 PM, Scott wrote: > Hello coreboot folks, > > I know the developers here use linux, but many other bios developers > are more comfortable with windows. Fortunately, it is easy to build > coreboot using a Windows machine. The example below demonstrates using > the curre

Re: [coreboot] Building coreboot BIOS on a Windows computer

Theis is very nice and probably needed in the long run. Mvh Anders - Reply message - Fra: "Patrick Georgi" Dato: tor., aug. 26, 2010 08:17 Emne: [coreboot] Building coreboot BIOS on a Windows computer Til: Am 26.08.2010 06:44, schrieb Scott: > Hello coreboot folks, &g

Re: [coreboot] Building coreboot BIOS on a Windows computer

Am 26.08.2010 06:44, schrieb Scott: > Hello coreboot folks, > > I know the developers here use linux, but many other bios developers > are more comfortable with windows. Fortunately, it is easy to build > coreboot using a Windows machine. The example below demonstrates using > the current coreboot

[coreboot] Building coreboot BIOS on a Windows computer

Hello coreboot folks, I know the developers here use linux, but many other bios developers are more comfortable with windows. Fortunately, it is easy to build coreboot using a Windows machine. The example below demonstrates using the current coreboot version, 5740. http://notabs.org/coreboot/core

Re: [coreboot] Trying to build MSI 6119 coreboot BIOS

Alex Buell wrote: > > Can you enable CONFIG_DEBUG_RAM_SETUP in Kconfig and reflash? > > If I could work out a way to boot the machine with Linux in order to > reflash.. ;) Is the flash chip socketed? If so you can flash that chip with the factory BIOS on another, compatible, mainboard. //Peter

Re: [coreboot] Trying to build MSI 6119 coreboot BIOS

On Tue, 2010-06-01 at 18:14 +0200, Stefan Reinauer wrote: > On 6/1/10 5:47 PM, Alex Buell wrote: > > OK, thanks for that one, I've now built CoreBoot and flashed it onto my > > MSI 6119 motherboard. Using serial console I can see the following > > > > core-boot-4.0-r5601 Tue Jun 1 14:41:35 BST 2010

Re: [coreboot] Trying to build MSI 6119 coreboot BIOS

On 6/1/10 5:47 PM, Alex Buell wrote: > OK, thanks for that one, I've now built CoreBoot and flashed it onto my > MSI 6119 motherboard. Using serial console I can see the following > > core-boot-4.0-r5601 Tue Jun 1 14:41:35 BST 2010 starting... > SMBus controller enabled > > Nothing else? Can yo

Re: [coreboot] Trying to build MSI 6119 coreboot BIOS

On Tue, 2010-06-01 at 15:16 +0200, Stefan Reinauer wrote: > On 6/1/10 2:54 PM, Alex Buell wrote: > > I've just downloaded and built SeaBIOS ready to use with CoreBoot on my > > old MSI 6119 motherboard. Unfortunately, CoreBoot is stopping with a > > build error in src/lib/uart8250.c with an undecla

Re: [coreboot] Trying to build MSI 6119 coreboot BIOS

On 6/1/10 2:54 PM, Alex Buell wrote: > I've just downloaded and built SeaBIOS ready to use with CoreBoot on my > old MSI 6119 motherboard. Unfortunately, CoreBoot is stopping with a > build error in src/lib/uart8250.c with an undeclared CONFIG_TTYS0_BASE > error on line 83. I have checked and seri

[coreboot] Trying to build MSI 6119 coreboot BIOS

I've just downloaded and built SeaBIOS ready to use with CoreBoot on my old MSI 6119 motherboard. Unfortunately, CoreBoot is stopping with a build error in src/lib/uart8250.c with an undeclared CONFIG_TTYS0_BASE error on line 83. I have checked and serial console output is definitely disabled in

Re: [coreboot] computers with Coreboot BIOS

I think that it sounds more like that they are offering it early at request untill thy (or otheres) gets it to work 100% and at that point they will just ship with it. -Anders lør, 01 05 2010 kl. 14:58 -0400, skrev Joseph Smith: > On 05/01/2010 10:12 AM, bari wrote: > > Joseph Smith wrote: > > >

Re: [coreboot] computers with Coreboot BIOS

On 05/01/2010 10:12 AM, bari wrote: Joseph Smith wrote: Free BIOS (Coreboot, etc.): --- Our computers are not yet available with a Free BIOS, but we are very interested in offering that option in the future. We can build systems with Coreboot as the BIOS, but there

Re: [coreboot] Indtast Bcc computers with Coreboot BIOS

For really practical use of coreboot the mainboards need to come loaded and supported from the vendor. That's what I've been pushing on for the last few years. And vendors are starting to listen -- not because of me, I suspect, but because of their other customers. There are Tier 1 vendors out the

[coreboot] Indtast Bcc computers with Coreboot BIOS

What about the video card limits? Mvh Anders - Reply message - Fra: "bari" Dato: lør., maj 1, 2010 16:12 Emne: [coreboot] computers with Coreboot BIOS Til: "Joseph Smith" Cc: , "Peter Link" Joseph Smith wrote: >&

Re: [coreboot] computers with Coreboot BIOS

Joseph Smith wrote: Free BIOS (Coreboot, etc.): --- Our computers are not yet available with a Free BIOS, but we are very interested in offering that option in the future. We can build systems with Coreboot as the BIOS, but there will be some limitations as to cert

Re: [coreboot] computers with Coreboot BIOS

On Fri, 30 Apr 2010 04:36:36 -0700 (PDT), Peter Link wrote: > Recently I inquired with Inatux Computers, which sells pre-installed > systems that include gNewSense and Trisquel, among others, about plans for > offering > coreboot BIOS as an option. > > After a few emails ba

[coreboot] computers with Coreboot BIOS

Recently I inquired with Inatux Computers, which sells pre-installed systems that include gNewSense and Trisquel, among others, about plans for offering coreboot BIOS as an option. After a few emails back and forth, they quickly added some information on their website on the following page

Re: [coreboot] BIOS RAM in AMD SB7XX southbridges ?

Darmawan Salihun wrote: > What is the BIOS RAM in AMD SB7XX used for? It will for example be used to store RAM configuration parameters when the system is suspended. > Is it to buffer the BIOS contents from SPI flash chip prior to > execution of the very first instruction? No. > I recall that

Re: [coreboot] BIOS RAM in AMD SB7XX southbridges ?

on 28/10/2009 06:55 Darmawan Salihun said the following: > On 10/28/09, Carl-Daniel Hailfinger wrote: >> On 27.10.2009 14:06, Darmawan Salihun wrote: >>> What is the BIOS RAM in AMD SB7XX used for? >>> >>> Is it to buffer the BIOS contents from SPI flash chip prior to >>> execution of the very fir

Re: [coreboot] BIOS RAM in AMD SB7XX southbridges ?

On 10/28/09, Carl-Daniel Hailfinger wrote: > On 27.10.2009 14:06, Darmawan Salihun wrote: >> What is the BIOS RAM in AMD SB7XX used for? >> >> Is it to buffer the BIOS contents from SPI flash chip prior to >> execution of the very first instruction? >> > > No. > > >> I recall that it's impossible

Re: [coreboot] BIOS RAM in AMD SB7XX southbridges ?

On 27.10.2009 14:06, Darmawan Salihun wrote: > What is the BIOS RAM in AMD SB7XX used for? > > Is it to buffer the BIOS contents from SPI flash chip prior to > execution of the very first instruction? > No. > I recall that it's impossible to execute code directly in an SPI chip. > Yes, bu

Re: [coreboot] BIOS RAM in AMD SB7XX southbridges ?

On 27.10.2009 21:51, David Hendricks wrote: > On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun wrote >> What is the BIOS RAM in AMD SB7XX used for? >> > > Looks like scratchpad memory to me. From the public > doc > : > > 3.3 BIOS R

Re: [coreboot] BIOS RAM in AMD SB7XX southbridges ?

On Tue, Oct 27, 2009 at 2:04 PM, Gregg Levine wrote: > On Tue, Oct 27, 2009 at 4:51 PM, David Hendricks > wrote: > > On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun > > wrote: > >> > >> What is the BIOS RAM in AMD SB7XX used for? > > > > Looks like scratchpad memory to me. From the public doc:

Re: [coreboot] BIOS RAM in AMD SB7XX southbridges ?

On Tue, Oct 27, 2009 at 4:51 PM, David Hendricks wrote: > On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun > wrote: >> >> What is the BIOS RAM in AMD SB7XX used for? > > Looks like scratchpad memory to me. From the public doc: > > 3.3 BIOS RAM > The SB700 has 256 bytes of BIOS RAM. Data in this

Re: [coreboot] BIOS RAM in AMD SB7XX southbridges ?

On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun < darmawan.sali...@gmail.com> wrote: > What is the BIOS RAM in AMD SB7XX used for? > Looks like scratchpad memory to me. From the public doc : 3.3 BIOS RAM The SB700 has 256 bytes of B

[coreboot] BIOS RAM in AMD SB7XX southbridges ?

What is the BIOS RAM in AMD SB7XX used for? Is it to buffer the BIOS contents from SPI flash chip prior to execution of the very first instruction? I recall that it's impossible to execute code directly in an SPI chip. or am I missing something? -- Regards, Darmawan Salihun ---

Re: [coreboot] BIOS POST codes monitoring in real time from other computer

2009/9/17 Antonio Expósito > I have seen the supported motherboard list/status, and there are several > VIA motherboards with chipsets of the same family but different models. > > Is it difficult to adapt one of them to my motherboard? (AMOS-3000 embedded > computer with P700 motherboard) > I wo

Re: [coreboot] BIOS POST codes monitoring in real time from other computer

for a new guy? This is my hobby, but I am really enthusiastic. Thanks, Antonio De: Myles Watson [mailto:myle...@gmail.com] Enviado el: jueves, 17 de septiembre de 2009 21:23 Para: Antonio Expósito CC: coreboot@coreboot.org Asunto: Re: [coreboot] BIOS POST codes monitoring in real

Re: [coreboot] BIOS POST codes monitoring in real time from other computer

Hi, On 17.09.2009 21:13, Antonio Expósito wrote: > I know that almost every BIOS sends them to the ISA I/O address 0080h, but, > how can I get that codes using another computer? I mean, without POST > ISA/PCI card, using another computer connected to it via SMBUS, LPC or > serial? > There are

Re: [coreboot] BIOS POST codes monitoring in real time from other computer

2009/9/17 Antonio Expósito > I am trying to monitor the boot process of a computer, mainly BIOS POST > codes and linux kernel boot process. I know how to do it for the linux > kernel using a serial port, but I am not able to imagine how to monitor the > BIOS POST codes. > > I know that almost ev

[coreboot] BIOS POST codes monitoring in real time from other computer

Hi all, I don’t want to disturb you with “newbie things”, but this is a way to start like another. I am trying to monitor the boot process of a computer, mainly BIOS POST codes and linux kernel boot process. I know how to do it for the linux kernel using a serial port, but I am not able to

Re: [coreboot] ### Bios

ron minnich wrote: On Wed, Nov 12, 2008 at 1:00 PM, Steve Spano <[EMAIL PROTECTED]> wrote: Hello Is anyone aware of a 2Mbyte PLCC32 BIOS flash prom that can be used with the AMD LX800 / CS5536? I would like to use coreboot V2 to directly launch the Linux kernel as an ELF payload and then use a

Re: [coreboot] ### Bios

Steve Spano wrote: > We using an SST/Pflash 512KB FWH device. Do you know the exact part number? I guess it's SST49LF004A or SST49LF004B, right? > I think SST is getting away from all FWH but could be wrong. I think they'll still keep the 8 and 16Mbit parts for a while. They have SST49LF008A wh

Re: [coreboot] ### Bios

On Wed, Nov 12, 2008 at 4:19 PM, Steve Spano <[EMAIL PROTECTED]> wrote: > Hello > > We using an SST/Pflash 512KB FWH device. I think SST is getting away from > all FWH but could be wrong. SST49LF016 is the FWH, I would bet you are using an SST49LF004 now. http://www.sst.com/downloads/datasheet/S71

Re: [coreboot] ### Bios

ssage- From: Tom Sylla [mailto:[EMAIL PROTECTED] Sent: Wednesday, November 12, 2008 4:30 PM To: [EMAIL PROTECTED] Cc: Peter Stuge; coreboot@coreboot.org Subject: Re: [coreboot] ### Bios On Wed, Nov 12, 2008 at 4:19 PM, Steve Spano <[EMAIL PROTECTED]> wrote: > Hello > > We using

Re: [coreboot] ### Bios

ident Finger Lakes Engineering -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Peter Stuge Sent: Wednesday, November 12, 2008 4:14 PM To: coreboot@coreboot.org Subject: Re: [coreboot] ### Bios Hi Steve, Steve Spano wrote: > Is anyone aware of a 2Mbyt

Re: [coreboot] ### Bios

coreboot@coreboot.org Subject: Re: [coreboot] ### Bios On Wed, Nov 12, 2008 at 1:00 PM, Steve Spano <[EMAIL PROTECTED]> wrote: > Hello > > Is anyone aware of a 2Mbyte PLCC32 BIOS flash prom that can be used > with the AMD LX800 / CS5536? > > I would like to use coreboot V2 to di

Re: [coreboot] ### Bios

On Wed, Nov 12, 2008 at 1:00 PM, Steve Spano <[EMAIL PROTECTED]> wrote: > Hello > > Is anyone aware of a 2Mbyte PLCC32 BIOS flash prom that can be used with the > AMD LX800 / CS5536? > > I would like to use coreboot V2 to directly launch the Linux kernel as an > ELF payload and then use a YAFFS2 fi

Re: [coreboot] ### Bios

Hi Steve, Steve Spano wrote: > Is anyone aware of a 2Mbyte PLCC32 BIOS flash prom that can be used > with the AMD LX800 / CS5536? Yes, at least SST have parts that fit. Depending on if you need LPC or FWH you can get the SST49LF160C or SST49LF016C parts. One of them is dual mode (both LPC and FW

[coreboot] ### Bios

Hello Is anyone aware of a 2Mbyte PLCC32 BIOS flash prom that can be used with the AMD LX800 / CS5536? I would like to use coreboot V2 to directly launch the Linux kernel as an ELF payload and then use a YAFFS2 filesystem to access a NAND flash on the IDE bus. Any thoughts would also be appre

Re: [coreboot] coreboot bios

On Tue, Oct 28, 2008 at 02:39:48AM -0700, Parts & Repair wrote: > Is there a Coreboot bios for the TP 600x? No, there's currently no such support, because this is a laptop and those are not yet supported by coreboot at all. This is due to technical reasons, for instance most lapto

[coreboot] coreboot bios

Is there a Coreboot bios for the TP 600x? Northbridge        Intel i440BX/ZX rev. C1 Mainboard Model        26454EU (0x19F - 0x44C0F5) Name            Intel Pentium III E Codename        Coppermine Specification        Package            MMC (platform ID = 3h) CPUID            6.8.1

[coreboot] Coreboot bios for a Thinkpad 600x, 2645-4eu ???

Hello, Please find the following info below to see if Coreboot has bios for my Tp 600x, 2645-4eu; I have included a lspci running Slackware 12.1 and below that I have a TEXT Dump from CPU-z 1.48 running XP from the same laptop, yes it's a dual boot box. [EMAIL PROTECTED]:/# lspci 00:00.0 Host

Re: [coreboot] Bios Debugging

Hans Schmid wrote: > General question: > Is there any reasonable way to debug BIOS code. I checked (almost) > everything like AMD's SimNow, Bochs, Qemu, hardware tools like > interposers and so on but they don't fit my expectations/requirements? > What I would need were a hardware based debugger

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