Re: [coreboot] Question about PCIe separate reference clock(solved)

2017-01-19 Thread Predrag Vidic
nks to you all. > > > Zheng > > > -- > *From:* Kyösti Mälkki > *Sent:* Friday, January 13, 2017 4:58 PM > *To:* Zheng Bao > *Cc:* Predrag Vidic; coreboot@coreboot.org; Zoran Stojsavljevic > *Subject:* Re: [coreboot] Question about PCIe sep

Re: [coreboot] Question about PCIe separate reference clock(solved)

2017-01-18 Thread Zheng Bao
crystal part and PCB layout, right? Kyösti From: Predrag Vidic mailto:pvi...@gmail.com>> Sent: Friday, January 13, 2017 10:29 AM To: Zheng Bao Cc: Zoran Stojsavljevic; coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] Question a

Re: [coreboot] Question about PCIe separate reference clock

2017-01-13 Thread Kyösti Mälkki
-- > *From:* Predrag Vidic > *Sent:* Friday, January 13, 2017 10:29 AM > > *To:* Zheng Bao > *Cc:* Zoran Stojsavljevic; coreboot@coreboot.org > *Subject:* Re: [coreboot] Question about PCIe separate reference clock > > Hi Zheng, > > Schematic is

Re: [coreboot] Question about PCIe separate reference clock

2017-01-13 Thread Zheng Bao
Does it mean the "on mainboard" side it does not support "Asynchronous clock mode"? Zheng From: Predrag Vidic Sent: Friday, January 13, 2017 10:29 AM To: Zheng Bao Cc: Zoran Stojsavljevic; coreboot@coreboot.org Subject: Re: [core

Re: [coreboot] Question about PCIe separate reference clock

2017-01-13 Thread Predrag Vidic
ojsavljevic; coreboot@coreboot.org > > *Subject:* Re: [coreboot] Question about PCIe separate reference clock > > Hi Zheng, > > Without knowing the particular solution for the PCIe transmitter you have > on your board, I'd check refclk pins on your design for the pro

Re: [coreboot] Question about PCIe separate reference clock

2017-01-12 Thread Zheng Bao
, 2017 9:22 AM To: Zheng Bao; Predrag Vidic Cc: coreboot@coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] Question about PCIe separate reference clock Hello Zheng, For decades, I've been FW/SW engineer, but I do understand a little bit of a HW. I have looked into t

Re: [coreboot] Question about PCIe separate reference clock

2017-01-12 Thread Predrag Vidic
rom:* Zoran Stojsavljevic > *Sent:* Thursday, January 12, 2017 9:22 AM > *To:* Zheng Bao; Predrag Vidic > *Cc:* coreboot@coreboot.org > *Subject:* Re: [coreboot] Question about PCIe separate reference clock > > Hello Zheng, > > For decades, I've been FW/SW engineer, but I d

Re: [coreboot] Question about PCIe separate reference clock

2017-01-12 Thread Zoran Stojsavljevic
board meet this requirement. So we doubt the problem > lies in PCI configration space. > > > Zheng > > > > From: Zoran Stojsavljevic > Sent: Thursday, January 12, 2017 9:22 AM > To: Zheng Bao; Predrag Vidic > Cc: coreboot@coreboot.org > Subject: Re: [co

Re: [coreboot] Question about PCIe separate reference clock

2017-01-12 Thread Kyösti Mälkki
On Thu, Jan 12, 2017 at 9:15 AM, Zheng Bao wrote: > Our VPX design uses separate reference clock source, which is Si52111-B5 > (No spread), instead of common ref clock from CPU. > > Now The system is unstable. Reading PCIE configuration space is unstable > too. (If we add some fly wire to make it

Re: [coreboot] Question about PCIe separate reference clock

2017-01-12 Thread Zheng Bao
about PCIe separate reference clock Hello Zheng, For decades, I've been FW/SW engineer, but I do understand a little bit of a HW. I have looked into the Si52111-B5 data sheet for clarification. My problem here is to understand, your use case: do you use local xtal attached to Si52111-

Re: [coreboot] Question about PCIe separate reference clock

2017-01-12 Thread Zoran Stojsavljevic
Hello Zheng, For decades, I've been FW/SW engineer, but I do understand a little bit of a HW. I have looked into the Si52111-B5 data sheet for clarification. My problem here is to understand, your use case: do you use local xtal attached to Si52111-B5 to generate local PCIe 25MHz clock? If you

[coreboot] Question about PCIe separate reference clock

2017-01-11 Thread Zheng Bao
Our VPX design uses separate reference clock source, which is Si52111-B5 (No spread), instead of common ref clock from CPU. Now The system is unstable. Reading PCIE configuration space is unstable too. (If we add some fly wire to make it work with common ref clock, the system becomes stable.) (