I wrote...
static const struct cnl_mb_cfg memcfg = {
…
};
Having been back and verified against the schematics, I have found a
couple of value that were incorrect.
spd[1] and spd[3] needed to the set to NOT_EXISTING and the designed is
not interleaved so .dq_pins_interleaved needed to be
Not sure about other ways for getting post code. May be EC can provide
that. Not sure to what extent DbC can help.
For now as Angel pointed out, along with SPD, dq_map, dqs_map,
Rcomp_resistor, Rcomp_Target.
I guess you have a CNL platform. Then for LPDDR4 memory, you can use
dq_map from
https:/
Naresh wrote...
To understand the exact failure cause in FSPM, you need to get post
code from FSP. What is printed in log is Coreboot post code only.
Is it possible to get the post code from FSPM without a hardware POST
code indicator?
The hardware I am using only has an M.2 slot (used for an
Angel wrote...
Well, I'd like to see your code: which memcfg parameters you're using,
among other things. Could you please put it somewhere (e.g.
review.coreboot.org) so that I can take a look?
I have basically just taken the memcfg structure from the Intel Comet
Lake reference platform and m
Hi Andy
On Wed, Nov 18, 2020 at 1:22 PM Andy Pont wrote:
>
> Angel wrote...
>
> I can’t match what is printed on the top of the Micron devices (two lines of
> text “0JE75” and “D9ZFW”) to any part numbers on Micron’s website. Is it some
> kind of encoded version of the part number or is it just
To understand the exact failure cause in FSPM, you need to get post code
from FSP. What is printed in log is Coreboot post code only.
Did you get memory part number from dmidecode -t 17 ?
If you read top of dimm, that will avoid confusion & in my experience
typically part number is printed. In some
Angel wrote...
I can’t match what is printed on the top of the Micron devices (two lines of
text “0JE75” and “D9ZFW”) to any part numbers on Micron’s website. Is it some
kind of encoded version of the part number or is it just factory and build
information? Looking at the website I would ass
Hi,
On Wed, Nov 18, 2020 at 10:00 AM Andy Pont wrote:
>
> Naresh wrote…
>
> Don't know how to recover SPD from UEFI but Try to read memory part number
> written on chip and provide that. Look for SPD file with that name if it's
> already present in coreboot.
>
> The schematics for the platform
Naresh wrote…
Don't know how to recover SPD from UEFI but Try to read memory part
number written on chip and provide that. Look for SPD file with that
name if it's already present in coreboot.
The schematics for the platform show Samsung K4A8G165WB-BCRC devices
which are (8Gb, 2400Mbps, 512Mx1
Don't know how to recover SPD from UEFI but Try to read memory part number
written on chip and provide that. Look for SPD file with that name if it's
already present in coreboot.
Regards,
Naresh solanki
On Mon, 16 Nov, 2020, 11:46 pm Matt DeVillier,
wrote:
> >
> src/soc/intel/cannonlake/romstag
>
src/soc/intel/cannonlake/romstage/fsp_params.c/mainboard_memory_init_params
called
means your board isn't overriding mainboard_memory_init_params() -- so all
the defaults are being used, which I'm not sure will result in a bootable
device. You might want to look at the CML/CFL reference boards,
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