can you assist to port on the tyan motherboard
lspci
00:01.0 PCI bridge: Broadcom HT1000 PCI/PCI-X bridge
00:02.0 Host bridge: Broadcom HT1000 Legacy South Bridge
00:02.1 IDE interface: Broadcom HT1000 Legacy IDE controller
00:02.2 ISA bridge: Broadcom HT1000 LPC Bridge
00:03.0 USB Controller: Br
Hi, I'm porting coreboot to tyan 3992 (HT2000/HT1000) using MSI MS9185
prebuild, if I right understand, all I need to do is edit Config.lb of
ms9185 build, with my platform lspci data, or maybe something else?
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Mikhail Savchenko wrote:
Hi, I’m porting coreboot to tyan 3992 (HT2000/HT1000) using MSI MS9185
prebuild, if I right understand, all I need to do is edit Config.lb of
ms9185 build, with my platform lspci data, or maybe something else?
Starting with Config.lb and maybe Options.lb in
src/main
Hello,
I have to port coreboot to a new "Mainboard" not listed in menuconfig.
Is there a basic "Mainboard" I should use as a starting point that will be
copied to my board ?
The file board_info.txt contains few parameters.
How can I know the meaning of each parameter and its possible values ?
Th
Pardon me for absurd questions, I am a noob. Is there any way to port
coreboot to my netbook without Intel FSP. Or is there any way I could
generate Intel FSP for my netbook? My netbook has Intel Atom N2600 CPU
which doesn't seem to have any Intel FSP available. Please, if there is any
guide to por
I have initialized Intel 82815 SDRAM controller but for a special type
of RAM without reading SPD registers. I know that DRP register is :
0xCC. I added the code to Coreboot.
I tested much and concluded that RAM has a problem in a way as you
guys told me before. When i change the hardwaremain() ,
Hi,
I suggest you read the wiki :
https://www.coreboot.org/Developer_Manual and
https://www.coreboot.org/Motherboard_Porting_Guide
I would also suggest maybe (optional) that you read my blog posts
about my own experience porting coreboot to a new motherboard :
https://puri.sm/posts/diving-back-int
Hello Youness,
Thank you very much for the detailed information !
Can you please tell what is the best starting point for a XEON board ?
I think there are no "Intel® XEON® Processor E3-1505M v5" boards in last
version of coreboot.
Am I right ?
Best regards,
Zvika
On Tue, May 29, 2018 at 9:15 PM
This is the best I can do for you :
https://ark.intel.com/products/89608/Intel-Xeon-Processor-E3-1505M-v5-8M-Cache-2_80-GHz
Product Collection: Intel® Xeon® Processor E3 v5 Family
Code Name: Products formerly Skylake
kakaroto@kakaroto:~/coding/purism/coreboot$ git grep SOC_INTEL_SKYLAKE
| grep m
Hi All,
The links you provided:
https://www.coreboot.org/Motherboard_Porting_Guide
https://www.coreboot.org/Developer_Manual
Does not mention Intel's FSP at all.
How FSP is integrated during coreboot porting ?
src\venorcode\intel contains 2 FSP versions.
src\soc\intel contains fsp_baytrail, fsp
Hello Zvika,
On 31.05.2018 04:39, Zvi Vered wrote:
> The links you provided:
> https://www.coreboot.org/Motherboard_Porting_Guide
> https://www.coreboot.org/Developer_Manual
>
> Does not mention Intel's FSP at all.
there is few FSP documentation maintained by the coreboot community.
But there ex
* ali hagigat [120214 18:48]:
> I have initialized Intel 82815 SDRAM controller but for a special type
> of RAM without reading SPD registers. I know that DRP register is :
> 0xCC. I added the code to Coreboot.
>
> I tested much and concluded that RAM has a problem in a way as you
> guys told me
reading your note leads me to believe you are not familiar with how
sdram startup works. It's a lot more than just setting one register.
ron
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we worked a few years back to remove all __asm__ stuff from coreboot
because it has so many tricky parts to making it work. If you're going
to write assembly, put it in a .s. a .c file should have C.
ron
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Hi Ron,
I've been looking for DDR-SDRAM start-up tutorial. Is there any on the
web outside of the JEDEC specs? Anyway, where are the codes located in
the Coreboot source ? is it on the motherboard-specific codes?
TIA,
Darmawan
On 2/15/12, ron minnich wrote:
> reading your note leads me to beli
Well, sorry about the noise. I forgot to mention that most of the RAM
init I found was in the raminit.c of each of the northbridge. Is there
any other important file(s) that I missed?
Thanks,
Darmawan
On 2/20/12, Darmawan Salihun wrote:
> Hi Ron,
>
> I've been looking for DDR-SDRAM start-up tut
you commented out a number of calls to critical functions. You can't
just simply set a register and assume it all works. Maybe I
misunderstood.
I think stepan's i945 code is a great example of how to turn on dram.
Or you can look at sdram_enable in the lx440 code for the basic sdram
startup cycle
Thanks Ron. I'm looking into it.
On 2/20/12, ron minnich wrote:
> you commented out a number of calls to critical functions. You can't
> just simply set a register and assume it all works. Maybe I
> misunderstood.
>
> I think stepan's i945 code is a great example of how to turn on dram.
> Or you
My RAM code was OK(I remember all the members of this mailing list
said:"your RAM initialization is not OK", if RAM is not OK how
"romstage", "ramstage" and now "filo" are being executed!! Hey, you'd
better take a closer look at the source code!!). The reason,
hardwaremain() could not be executed,
On Tue, Mar 27, 2012 at 2:23 AM, ali hagigat wrote:
> My RAM code was OK(I remember all the members of this mailing list
> said:"your RAM initialization is not OK", if RAM is not OK how
> "romstage", "ramstage" and now "filo" are being executed!!
I've had this work with RAM that is not OK.
> Now
Thank you, Ron, for the reply.
I have checked RAM by one assembly code i developed, the whole code
has been written by myself(it is not Coreboot). I tested RAM ,
particularly the first 5 mega bytes by read/write cycles and "mov"
instructions.
I even had a serial port code in EPROM , i copied that t
On Wed, 2012-03-28 at 13:51 +0430, ali hagigat wrote:
> I remember when i ported my RAM initialization code, hardwaremain()
> could not be run. The problem was not RAM, it was CPU! i chaned
> c_start() a bit to solve the problem.
> What do you mean by earlyprintk(), do you suggest to change linux
>
ali hagigat wrote:
> Besides I checked RAM by ramcheck() function of Coreboot.
This means nothing.
> I will test it finally by memtest().
Do two instances of testing, one with memtest86, one with memtest86+.
> But i am believing that the problem is some where else.
Yes this is obvious to eve
Hello,
I'd like to port coreboot to a motherboard I have. I dont have either
brand or model (it's a generic OEM board).
I'm not sure what info is needed so I have uploaded:
lspci -xxxvvvnnn http://pastebin.org/876731
superiotool -deV http://pastebin.org/876714
I'd like to know if it's poss
Hello,
I'd like to port coreboot to a motherboard I have. I dont have either
brand or model (it's a generic OEM board).
I'm not sure what info is needed so I have uploaded:
lspci -xxxvvvnnn http://pastebin.org/876731
superiotool -deV http://pastebin.org/876714
I'd like to know if it's poss
Hello,
I created a new mainboard based on "Bayley Bay FSP-based CRB"
It seems that (at least) the following files are mandatory for build:
cmos.layout
devicetree.cb
romstage.c
Am I right ?
If yes - what info required to write those files ?
Can I use coreboot default files instead ?
Honestly - I
Hi!
I need help to porting coreboot Asus M4a785m on Asus M5a78l-m lx3.
I'm trying to porting coreboot on the motherboard Asus M5a78l-m lx3
(rs780l/sb710). I cannot find documentation for the northbridge rs780l.
My configuration: cpu - Athlon 2 x2 220 (K10), memory - 2 + 2 Gb DDR3, video -
Asu
Hey All,
is anyone interested in porting coreboot to solidpc:
http://wiki.solid-run.com/doku.php?id=products:ibx:solidpc
I can provide some free hardware samples for developers.
just let me know
kind regards
Malte
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https://www.coreboot.org/mailma
This board is a hard one to start out with i would say.
You should look in to getting the documentation for the SIS 620 chip
set. I see that the SIS 630 is supported by Coreboot v1 so you might
want to look in to porting that to v4 and then the SIS 620.
-Anders
ons, 15 09 2010 kl. 18:30 -0300, s
În Vin, Septembrie 17, 2010 2:44, Anders Jenbo a scris:
> This board is a hard one to start out with i would say.
>
>
> You should look in to getting the documentation for the SIS 620 chip
> set. I see that the SIS 630 is supported by Coreboot v1 so you might want
> to look in to porting that to v4
Here's a photo of the board in question
http://yfrog.com/5g20100917104133116resistj
On Fri, Sep 17, 2010 at 4:01 AM, Cristi Magherusan
wrote:
> În Vin, Septembrie 17, 2010 2:44, Anders Jenbo a scris:
>> This board is a hard one to start out with i would say.
>>
>>
>> You should look in to getti
Zvika:
You are lucky If the model of your board appears in the list of supported
nodels because you have to do not much, but, if not, you have to do a
"motherboard porting" for your specific system.
Is essential you add the correct microcode and configure correctly FSP on
memory settings otherw
to properly install
the necessary bits for gfx.
Thanks for any help.
From: Алексей Боровиковvia coreboot
Sent: Thursday, May 19, 2016 9:43 PM
To: coreboot@coreboot.org
Subject: [coreboot] Porting coreboot on ASUS M5A78L-M LX3
Hi!
I need help to porting coreboot Asus M4a785m on Asus M5a78l-m
bject: Re: [coreboot] Porting coreboot on ASUS M5A78L-M LX3
I was able to start up the internal graphics core, but unfortunately only in
text mode. I think the problem in the initialization in funcution -
internal_gfx_pci_dev_init and rs780_internal_gfx_enable
(src\southbridge\amd\rs780\gfx.c)
Hello everyone,
I am trying to port coreboot to the Asus P5G41T-M LX motherboard but I
got stuck.
This motherboard has:
- Northbridge: Intel G41
- Southbridge: ICH7
- Super IO: w83627dhg
I used the Gigabye GA-G41M-ES2L code as base since I think it has the
same north- and southbridge. That mo
We are considering to port Coreboot for Intel Atom E660 + EG20T chipset
patform. Our platform base on Intel Crown Bay evaluation board.
I wonder what are the first steps of porting?
What should we start to work from?
Any manuals, documents, suggestions, etc?
Thanks
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coreboot mailing list: c
Hi,
I have a Atom Silverthorne Poulsbo based board
(http://www.iwavesystems.com/iW-Q7.htm). I want to port coreboot on this
platform.
I would like to know if anybody has started/suceeded in porting coreboot to
Atom, also if there is anyone interested in such a port.
I saw two threads in m
Hi Martin,
Autoport wasn't much use to me since it didn't recognize anything.
However it left behind all kinds of logs like the full lspci output and
stuff like that -> that's why I shared it.
https://github.com/rnplus/test-coreboot-for-asus-p5g41t-m-lx/blob/maste
r/superiodump
https://github.co
Ok, looking at the differences between your code ant the GA-G41M code, I
think you might want to add back in the ich7_enable_lpc() function (or
something equivalent) . My guess is that you're not sending the necessary
IO ports out to LPC.
Martin
On Mon, Mar 21, 2016 at 2:25 PM, Renze Nicolai wr
Hi Martin,
I added back that function and tried changing / adding some other stuff
and guess what? Serial console works! Thank you for pointing in the
right direction.
Now the next problem: this motherboard uses an Intel X4X northbridge
with DDR3 RAM.
This is the serial console output:
=
Hello Mansoor, welcome to the coreboot community!
Mansoor wrote:
> I have a Atom Silverthorne Poulsbo based board
> (http://www.iwavesystems.com/iW-Q7.htm).
> I want to port coreboot on this platform.
That's wonderful!
> I would like to know if anybody has started/suceeded in porting
> coreb
Mansoor wrote:
Hi,
I have a Atom Silverthorne Poulsbo based board
(http://www.iwavesystems.com/iW-Q7.htm). I want to port coreboot on this
platform.
I would like to know if anybody has started/suceeded in porting coreboot
to Atom, also if there is anyone interested in such a port.
There
On Tue, 14 Apr 2009 08:56:06 -0500, bari wrote:
> Mansoor wrote:
>> Hi,
>>
>> I have a Atom Silverthorne Poulsbo based board
>> (http://www.iwavesystems.com/iW-Q7.htm). I want to port coreboot on this
>> platform.
>>
>> I would like to know if anybody has started/suceeded in porting coreboot
>
: "Joseph Smith"
To: "bari"
Cc: "Mansoor" ;
Sent: Tuesday, April 14, 2009 7:45 PM
Subject: Re: [coreboot] Porting coreboot to Intel Atom (Silverthorne) &
SCH US15W (Poulsbo) chipset
On Tue, 14 Apr 2009 08:56:06 -0500, bari wrote:
Mansoor wrote:
Hi,
I have
bari wrote:
> There are several i945 + Atom boards available. This way you can
> develop and test Atom on a working chipset and then work on the
> US15W.
In my opinion, porting US15W may not be worthwhile, since it doesn't
support the SPI bus which would allow use of SPI NOR flash. US15W
suppor
On Wed, 15 Apr 2009 17:40:56 -0500, wrote:
> bari wrote:
>
>> There are several i945 + Atom boards available. This way you can
>> develop and test Atom on a working chipset and then work on the
>> US15W.
>
> In my opinion, porting US15W may not be worthwhile, since it doesn't
> support the SPI b
On Wed, Apr 15, 2009 at 6:40 PM, wrote:
> The i945/ICH7M would be a far better final target for an Atom chipset
> and has none of the above mentioned issues. Of course you would need
> to use Diamondville Atom rather Silverthorne Atom in this case.
>
The problem with i945, from what I've read,
On Wed, 15 Apr 2009 19:51:59 -0400, Corey Osgood
wrote:
> On Wed, Apr 15, 2009 at 6:40 PM, wrote:
>
>> The i945/ICH7M would be a far better final target for an Atom chipset
>> and has none of the above mentioned issues. Of course you would need
>> to use Diamondville Atom rather Silverthorne
On Thu, 16 Apr 2009 00:39:30 -0400, Joseph Smith
wrote:
>
>
>
> On Wed, 15 Apr 2009 19:51:59 -0400, Corey Osgood
> wrote:
>> On Wed, Apr 15, 2009 at 6:40 PM, wrote:
>>
>>> The i945/ICH7M would be a far better final target for an Atom chipset
>>> and has none of the above mentioned issues.
> On Wed, 15 Apr 2009 17:40:56 -0500, wrote:
...
>> Good luck with your Poulsbo (US15W) port, assuming you are willing to
>> spend 6-9 months on it. It could be more or less than that depending
>> on the number of people working on it and their firmware experience.
Joseph Smith wrote:
> Hey thi
hi,
a view weeks ago i read about the start of a menlow port.
has anybody started the port?
Br, stefan
On Tue, 14 Apr 2009 08:56:06 -0500, bari wrote:
> Mansoor wrote:
>> Hi,
>>
>> I have a Atom Silverthorne Poulsbo based board
>> (http://www.iwavesystems.com/iW-Q7.htm). I want to port coreb
On Mon, 1 Jun 2009 20:49:24 +0200, "Gaechter, Stefan"
wrote:
> hi,
>
> a view weeks ago i read about the start of a menlow port.
> has anybody started the port?
>
> Br, stefan
>
>
>
> On Tue, 14 Apr 2009 08:56:06 -0500, bari wrote:
>> Mansoor wrote:
>>> Hi,
>>>
>>> I have a Atom Silverth
Gaechter, Stefan wrote:
hi,
a view weeks ago i read about the start of a menlow port.
has anybody started the port?
I don't think anyone has specs yet.
-Bari
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http://www.coreboot.org/mailman/listinfo/coreboot
On 05.06.2009 15:51 Uhr, bari wrote:
> Gaechter, Stefan wrote:
>> hi,
>>
>> a view weeks ago i read about the start of a menlow port.
>> has anybody started the port?
>
> I don't think anyone has specs yet.
>
> -Bari
>
coresystems does.
Best regards,
Stefan
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