Re: [coreboot] use gcc 4.6.0 link time optimization to reduce coreboot execution time

2011-05-02 Thread Scott Duplichan
Kevin O'Connor wrote: ] Here seabios kconfig options I changed: ][...] ] ATA controllers n ] AHCI controllers y ] Floppy controllern ] PS/2 portn ] USB UHCI controllers

Re: [coreboot] use gcc 4.6.0 link time optimization to reduce coreboot execution time

2011-05-01 Thread Kevin O'Connor
On Sat, Apr 30, 2011 at 10:37:09PM -0500, Scott Duplichan wrote: Kevin O'Connor wrote: ] That's a great boot time! Do you have a breakdown of where the 640ms ] is spent? I tried adding some serial logging to get an idea about where the time is spent. The logging adds 8 ms to the boot time:

Re: [coreboot] use gcc 4.6.0 link time optimization to reduce coreboot execution time

2011-04-30 Thread Kevin O'Connor
On Thu, Apr 28, 2011 at 10:01:50PM -0500, Scott Duplichan wrote: The option is off by default because of side effects such as long build time and unusable dwarf2 debug output. This option cuts persimmon+seabios DOS boot from SSD time from 690 ms to 640 ms. That's a great boot time! Do you

Re: [coreboot] use gcc 4.6.0 link time optimization to reduce coreboot execution time

2011-04-30 Thread Scott Duplichan
Kevin O'Connor wrote: ] That's a great boot time! Do you have a breakdown of where the 640ms ] is spent? ] ] -Kevin Hello Kevin, I tried adding some serial logging to get an idea about where the time is spent. The logging adds 8 ms to the boot time: Time in ms 0 cold reset 366memory

Re: [coreboot] use gcc 4.6.0 link time optimization to reduce coreboot execution time

2011-04-29 Thread Rudolf Marek
image size by removing unused functions and data. Reducing the image size saves boot time by minimizing the flash memory read It always made me wonder how DMA support for flash memory copy could improve this. The SB700/SB800 has a support for that - it allows to copy the flash memory using

[coreboot] use gcc 4.6.0 link time optimization to reduce coreboot execution time

2011-04-28 Thread Scott Duplichan
Adds a kconfig option to enable gcc link time optimization. Link time optimization reduces both rom stage and ram stage image size by removing unused functions and data. Reducing the image size saves boot time by minimizing the flash memory read and decompress time for ram stage. The option is

Re: [coreboot] use gcc 4.6.0 link time optimization to reduce coreboot execution time

2011-04-28 Thread Stefan Reinauer
On 4/28/11 8:01 PM, Scott Duplichan wrote: Adds a kconfig option to enable gcc link time optimization. Link time optimization reduces both rom stage and ram stage image size by removing unused functions and data. Reducing the image size saves boot time by minimizing the flash memory read and

Re: [coreboot] use gcc 4.6.0 link time optimization to reduce coreboot execution time

2011-04-28 Thread Scott Duplichan
Stefan Reinauer wrote: ] Did you do some size tests with non-AGESA targets? The improvement for non-agesa-v5 projects is smaller. Here are a couple of examples: AMD Mahogany F10 standard -flto fallback/romstage 74803 73004 fallback/coreboot_ram 55665 49928 Intel D945GCLF