Re: [cryptography] Which encryption chips are compromised?

2013-11-10 Thread James Cloos
perhaps something can be found by analyzing it as pixel data? Or perhaps the variation is just a combination of quantum noise from the scan and jpeg/DCT artifacts? -JimC -- James Cloos OpenPGP: 1024D/ED7DAEA6 ___ cryptography mailing li

Re: [cryptography] NSA IDA Cryptological Research Centers

2013-09-29 Thread James Cloos
c programming". THe application the cryptography is probably something to do with statistical cryptanalysis. Rainbow tables, maybe? -JimC -- James Cloos OpenPGP: 1024D/ED7DAEA6 ___ cryptography mailing list cryptography@randombit.net http://lists.randombit.net/mailman/listinfo/cryptography

Re: [cryptography] Paypal phish using EV certificate

2013-08-13 Thread James Cloos
l from their transaction report mail. Separation of important mail from marketing mail by using different domains for each is a common tactic in the control-spam-but-get-the- important-automated-mail-through community. -JimC -- James Cloos OpenPGP: 1024D/ED7DAEA6

Re: [cryptography] openssl on git

2013-01-28 Thread James Cloos
is arguably dumb is storing that backup on a public site. *Any* public site. And unencrypted at that. This seems to be another case of thoughtless "everything to the cloud" (said with a Q♥-off-with-their-heads sort of tone). ;^/ I'm pretty sure hg and bzr also require the repo

Re: [cryptography] openssl on git

2013-01-01 Thread James Cloos
code for cvs2git combined with the patch he posted today (on git@vger) for git's cvsimport might prove best. His other posts to git@vger over the past week or two give the best details. -JimC -- James Cloos OpenPGP: 1024D/ED7DAEA6 ___

Re: [cryptography] Intel RNG

2011-06-18 Thread James Cloos
32-bit or 64-bit modes and the use of 0x48|0x41 (aka 0x49) to access the gp registers r8-r15 as 64-bit registers. It'll be interesting to see what AMD does on this front. -JimC -- James Cloos OpenPGP: 1024D/ED7DAEA6 ___ cryptography m

Re: [cryptography] Intel RNG

2011-06-18 Thread James Cloos
and with a REX.W prefix to specify any of the 64-bit registers. Based on p B-10 of that pdf, the Exx registers are ordered eAX, eCX, eDX, eBX, eSP, eBP, eSI, eDI. The REX.B prefix is 0x41 and REX.W is 0x48. I think that means that 41 0F C7 F1 would randomize 32-bit R9 and 48 0F C7 F2 (64-bit

Re: [cryptography] Intel RNG

2011-06-18 Thread James Cloos
>>>>> "JC" == James Cloos writes: JC> and, in 16-bit code: JC> RDRAND al ; randomize 16-bit register al Eeek. Thinko there. Please s/al/ax/. al and ah are the 8-bit halves of the 16-bit ax register. (Thanks to JW for noticing.) -JimC -- Jame

Re: [cryptography] Intel RNG

2011-06-17 Thread James Cloos
AND rdx ; randomize 64-bit register rax and, in 16-bit code: RDRAND al ; randomize 16-bit register al -JimC -- James Cloos OpenPGP: 1024D/ED7DAEA6 ___ cryptography mailing list cryptography@randombit.net http://lists.randombit.net/mailman/listinfo/cryptography