I have used UBIFS as i have 256MB of FLASH but i have to save my changes to the
flash when i do mkdir 123 the directory is created but when i reset the board
the directory isn't there.however when i reset board after few seconds then the
directory is dere after reset can anyone tell me what is
Hi,all
Is there any documents about the lens distortion of DM36x,I want to use
DM368 to interface a fisheye lens,
so I must use the lens distortion module to calibrate the image.
Any tips or help will be appreciated!
Thank you!
btw:How can I perform AE and AWB opration on DM368,there is not a 3A
Using sync option solves the problem but it is not recomended
--- On Thu, 15/7/10, rohan tabish rohan_ja...@yahoo.co.uk wrote:
From: rohan tabish rohan_ja...@yahoo.co.uk
Subject: Problem with UBIFS
To: davinci-linux-open-source@linux.davincidsp.com
Date: Thursday, 15 July, 2010, 11:00
I have
Hi,
I'm searching for a possibility to figure out which reset source caused
a system reset! Is there a way to do that?
I don't know if there is a register or something like that which stores
the reset condition. I would like to distinguish between a watchdog
reset and a normal reboot! Is
On Thu, Jul 15, 2010 at 08:09:04AM +0200, davide.bonfa...@bticino.it wrote:
Per: Raffaele Recalcati lamiapost...@gmail.com
Da: Mark Brown broo...@opensource.wolfsonmicro.com
Data: 14/07/2010 16.44
You might want to look at your MUA configuration here - it's sending
stuff with broken line
Sudhakar Rajashekhara wrote:
On TI's DA830/OMAP-L137, DA850/OMAP-L138 and DM365, after setting the
4BITECC_ADD_CALC_START bit in the NAND Flash control register to 1 and
before waiting for the NAND Flash status register to be equal to 1, 2
or 3, we have to wait till the ECC HW goes to
Hi,
On Thu, Jul 15, 2010 at 16:31:19, Jon Povey wrote:
Sudhakar Rajashekhara wrote:
On TI's DA830/OMAP-L137, DA850/OMAP-L138 and DM365, after setting the
4BITECC_ADD_CALC_START bit in the NAND Flash control register to 1 and
before waiting for the NAND Flash status register to be equal to
On Thu, Jul 15, 2010 at 17:11:32, Sudhakar Rajashekhara wrote:
Hi,
On Thu, Jul 15, 2010 at 16:31:19, Jon Povey wrote:
Sudhakar Rajashekhara wrote:
On TI's DA830/OMAP-L137, DA850/OMAP-L138 and DM365, after setting the
4BITECC_ADD_CALC_START bit in the NAND Flash control register to 1
Currently the EDMA queue to be used by for servicing ASP through
internal RAM is fixed to EDMAQ_0 and that to service internal RAM
from external RAM is fixed to EDMAQ_1.
This may not be the desirable configuration on all platforms. For
example, on DM365, queue 0 has large fifo size and is more
On Thu, Jul 15, 2010 at 2:32 AM, rohan tabish rohan_ja...@yahoo.co.ukwrote:
Using sync option solves the problem but it is not recomended
According to
http://www.linux-mtd.infradead.org/doc/ubifs.html
You can use fsync in the application to force write-through for specific
files while having
From: Davide Bonfanti davide.bonfa...@bticino.it
Clockout2 is added as a child of pll1_sysclk9, because they have
the same pll divisor.
Added dm365_clkout2_set_rate to properly set clockout2 frequency.
Modified the davinci_set_sysclk_rate function in order
to get the right
Please not consider this patch.
I have to re-check it.
I'm sorry for the mistake.
2010/7/14 Raffaele Recalcati lamiapost...@gmail.com
From: Davide Bonfanti davide.bonfa...@bticino.it
Added also possibility to set sysclk frequency.
Added possibility to set clockout2 frequency.
On Wed, Jul 14, 2010 at 04:28:10PM +0200, Raffaele Recalcati wrote:
From: Davide Bonfanti davide.bonfa...@bticino.it
Since DM365 has the same DMA event for McBSP and Voicecodec this two
peripherals cannot be used at the same time.
Please try to format your patches as documented in
From: Tharmarajan Ganeshan [mailto:tha...@e-consystems.com]
Sent: Wednesday, July 14, 2010 8:17 AM
To: Tivy, Robert
Cc: davinci-linux-open-source@linux.davincidsp.com; maharajan; dhineshkumar
Subject: RE: DM355 - 256MB RAM memory issue
Hi Robert,
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