inux.davincidsp.com
Sent: Thursday, January 18, 2007 12:48:58 PM
Subject: RE: Can the ARM and DSP accessing the RAM simulatenously?
Hi Folks,
Maybe to help clarify this a bit from my point of view
1) You can only have one-bit of data from one point in memory on the
traces for the DDR at any t
Behalf Of
Griffis, Brad
Sent: Thursday, January 18, 2007 3:13 PM
To: Andy Ngo; Azbell, Brandon;
davinci-linux-open-source@linux.davincidsp.com
Subject: RE: Can the ARM and DSP accessing the RAM simulatenously?
Juan is discussing this from a Linux threads perspective, not the actual
interface
: Thursday, January 18, 2007 1:50 PM
To: Griffis, Brad; Azbell, Brandon;
davinci-linux-open-source@linux.davincidsp.com
Subject: Re: Can the ARM and DSP accessing the RAM simulatenously?
Hmm..., I just received an answer from a TI expert that says that the ARM and
DSP can still access the DDR
al Message
From: "Griffis, Brad" <[EMAIL PROTECTED]>
To: Andy Ngo <[EMAIL PROTECTED]>; davinci-linux-open-source@linux.davincidsp.com
Sent: Thursday, January 18, 2007 9:27:36 AM
Subject: RE: Can the ARM and DSP accessing the RAM simulatenously?
Andy,
You are correct that
re-use of code/data.
Brad
From: Andy Ngo [mailto:[EMAIL PROTECTED]
Sent: Thursday, January 18, 2007 4:16 AM
To: Griffis, Brad; Azbell, Brandon;
davinci-linux-open-source@linux.davincidsp.com
Subject: Re: Can the ARM and DSP accessing the RAM simulatenously
: Wednesday, January 17, 2007 6:12:07 PM
Subject: RE: Can the ARM and DSP accessing the RAM simulatenously?
Andy,
Perhaps the following info will help you
in deciding whether to add a second RAM device.
Keep in mind that both the ARM and DSP have
cache. The cac
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Azbell, Brandon
Sent: Wednesday, January 17, 2007 7:54 PM
To: Andy Ngo; davinci-linux-open-source@linux.davincidsp.com
Subject: RE: Can the ARM and DSP accessing the RAM simulatenously?
Andy,
The DM6446 has exactl
Andy,
The DM6446 has exactly 2 memory interface busses on it. One
interfaces to DD2 memories and the other is the EMIFA, which can support
Asynchronous SRAM and Flash.
These 2 memory interfaces are completely independent of each other. At any
given moment in time, one and only
