On Sat, 28 May 2022 17:32:52 +0800
Min Zhou wrote:
> This patch adds spinlock operations for LoongArch architecture.
> These implementations refer to GLIBC pthread_spin_xxlock(). The
> underlying implementation is based on LoongArch atomic
> instructions (ie, AMSWAP_DB.W).
>
> Signed-off-by: Min
On Sat, 28 May 2022 17:32:48 +0800
Min Zhou wrote:
> This patch adds architecture specific atomic operations for
> LoongArch architecture.
>
> Signed-off-by: Min Zhou
DPDK has adopted std atomics. Could you please fix your toolchain
to support that instead.
24/05/2022 21:14, Honnappa Nagarahalli пишет:
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16/05/2022 07:10, Feifei Wang пишет:
Curren
27/05/2022 14:45, Harry van Haaren пишет:
Small improvements to the documentation based on Sphinx HTML doc output.
Signed-off-by: Harry van Haaren
---
Cc: konstantin.v.anan...@yandex.ru
---
doc/guides/prog_guide/bpf_lib.rst | 8
1 file changed, 4 insertions(+), 4 deletions(-)
di
This patch adds claim responsibility for LoongArch architecture.
Signed-off-by: Min Zhou
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 17a0559ee7..69ea00cddf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -269,6 +269,15 @@ F: lib/eal/
This patch adds system call number of memfd_create for LoongArch
architecture.
Signed-off-by: Min Zhou
---
drivers/net/memif/rte_eth_memif.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/memif/rte_eth_memif.h
b/drivers/net/memif/rte_eth_memif.h
index a5ee23d42e
The purpose of this patch is used to fix building issues for
LoongArch architecture. The hardware instructions based vector
implementation will come in a future patch.
Signed-off-by: Min Zhou
---
drivers/net/ixgbe/ixgbe_rxtx_vec_lsx.c | 60 ++
drivers/net/ixgbe/meson.buil
The hardware instructions based vector implementation will come
in a future patch. This dummy implementation can also work.
Signed-off-by: Min Zhou
---
app/test/test_xmmt_ops.h | 17 ++
lib/lpm/meson.build | 1 +
lib/lpm/rte_lpm.h| 2 +
lib/lpm/rte_lpm_lsx.h| 129 ++
The purpose of this patch is used to fix building issues for
LoongArch architecture. The hardware instructions based vector
implementation will come in a future patch.
Signed-off-by: Min Zhou
---
drivers/net/i40e/i40e_rxtx_vec_lsx.c | 54
drivers/net/i40e/meson.build
This patch adds system call number of bpf for LoongArch
architecture.
Signed-off-by: Min Zhou
---
drivers/net/tap/tap_bpf.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/tap/tap_bpf.h b/drivers/net/tap/tap_bpf.h
index f0b9fc7a2c..b1c9600ed8 100644
--- a/drivers/
This patch sets a different eal base address for LoongArch
architecture.
Signed-off-by: Min Zhou
---
lib/eal/linux/eal_memory.c | 4
1 file changed, 4 insertions(+)
diff --git a/lib/eal/linux/eal_memory.c b/lib/eal/linux/eal_memory.c
index c890c42106..60fc8cc6ca 100644
--- a/lib/eal/linux/
This patch adds some meson.build files for building DPDK on
LoongArch architecture.
Signed-off-by: Min Zhou
---
.../loongarch/loongarch_loongarch64_linux_gcc | 16 +++
config/loongarch/meson.build | 46 +++
lib/eal/loongarch/include/meson.build | 21 +
This patch adds hypervisor operations for LoongArch architecture.
In fact, these operations are currently not supported on LoongArch.
Signed-off-by: Min Zhou
---
lib/eal/loongarch/rte_hypervisor.c | 11 +++
1 file changed, 11 insertions(+)
create mode 100644 lib/eal/loongarch/rte_hyperv
LoongArch architecture has a different huge page size (32MB) than
other architectures. This patch adds a new huge page size for
LoongArch architecture.
Signed-off-by: Min Zhou
---
lib/eal/include/rte_memory.h | 1 +
lib/eal/include/rte_memzone.h | 1 +
2 files changed, 2 insertions(+)
diff --g
This patch adds power operations for LoongArch architecture. In
fact, these operations are temporarily not supported on LoongArch.
Signed-off-by: Min Zhou
---
.../loongarch/include/rte_power_intrinsics.h | 20
lib/eal/loongarch/rte_power_intrinsics.c | 51 +++
2 fi
This patch adds mcslock operations for LoongArch architecture.
Let it uses generic mcslock implementation.
Signed-off-by: Min Zhou
---
lib/eal/loongarch/include/rte_mcslock.h | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 lib/eal/loongarch/include/rte_mcslock.h
di
This patch adds pflock operations for LoongArch architecture.
Let it uses generic pflock implementation.
Signed-off-by: Min Zhou
---
lib/eal/loongarch/include/rte_pflock.h | 17 +
1 file changed, 17 insertions(+)
create mode 100644 lib/eal/loongarch/include/rte_pflock.h
diff --
This patch adds ticketlock operations for LoongArch architecture.
Let it uses generic ticketlock implementation.
Signed-off-by: Min Zhou
---
lib/eal/loongarch/include/rte_ticketlock.h | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 lib/eal/loongarch/include/rte_tick
This patch adds rwlock operations for LoongArch architecture.
The implementation is based on lib/eal/ppc/include/rte_rwlock.h.
Signed-off-by: Min Zhou
---
lib/eal/loongarch/include/rte_rwlock.h | 42 ++
1 file changed, 42 insertions(+)
create mode 100644 lib/eal/loongarc
The hardware instructions based vector implementation for memcpy
will come later. At present, this dummy implementation can also
work.
Signed-off-by: Min Zhou
---
lib/eal/loongarch/include/rte_memcpy.h | 193 +
lib/eal/loongarch/include/rte_vect.h | 47 ++
2 files
This patch adds architecture specific pause operations for
LoongArch architecture.
Signed-off-by: Min Zhou
---
lib/eal/loongarch/include/rte_pause.h | 24
1 file changed, 24 insertions(+)
create mode 100644 lib/eal/loongarch/include/rte_pause.h
diff --git a/lib/eal/loo
This patch adds io operations for LoongArch architecture. Let it
uses generic I/O implementation.
Signed-off-by: Min Zhou
---
lib/eal/loongarch/include/rte_io.h | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 lib/eal/loongarch/include/rte_io.h
diff --git a/lib/eal/
This patch uses aux vector software register to get CPU flags
and add CPU flag checking support for LoongArch architecture.
Signed-off-by: Min Zhou
---
lib/eal/loongarch/include/rte_cpuflags.h | 39 ++
lib/eal/loongarch/rte_cpuflags.c | 94
2 files change
This patch adds spinlock operations for LoongArch architecture.
These implementations refer to GLIBC pthread_spin_xxlock(). The
underlying implementation is based on LoongArch atomic
instructions (ie, AMSWAP_DB.W).
Signed-off-by: Min Zhou
---
lib/eal/loongarch/include/rte_spinlock.h | 93 +++
This patch adds architecture specific prefetch operations
for LoongArch architecture.
Signed-off-by: Min Zhou
---
lib/eal/loongarch/include/rte_prefetch.h | 47
1 file changed, 47 insertions(+)
create mode 100644 lib/eal/loongarch/include/rte_prefetch.h
diff --git a/li
This patch adds architecture specific atomic operations for
LoongArch architecture.
Signed-off-by: Min Zhou
---
lib/eal/loongarch/include/rte_atomic.h | 401 +
1 file changed, 401 insertions(+)
create mode 100644 lib/eal/loongarch/include/rte_atomic.h
diff --git a/lib/e
Dear team,
The following patch set is intended to support DPDK running on LoongArch
architecture.
LoongArch is the general processor architecture of Loongson and is a new RISC
ISA, which is a bit like MIPS or RISC-V.
The online documents of LoongArch are here:
https://loongson.github.io/L
This patch adds architecture specific byte order operations
for LoongArch architecture. LoongArch bit designations are
always little-endian.
Signed-off-by: Min Zhou
---
lib/eal/loongarch/include/rte_byteorder.h | 46 +++
1 file changed, 46 insertions(+)
create mode 100644 li
This patch adds architecture specific cpu cycle operations for
LoongArch. The RDTIME.D instruction is used to read constant
frequency timer information including counter value. The CPUCFG
instruction is used to dynamically identify which features of
LoongArch are implemented in the running processo
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