Thanks David for taking over this job.
> -Original Message-
> From: David Christensen
> Sent: Thursday, March 28, 2019 6:32 AM
> To: chao...@linux.vnet.ibm.com
> Cc: dev@dpdk.org; David Christensen
> Subject: [PATCH] maintainers: Succeed Chao Zhu as maintainer of E
Dekel£¬
To control the memory order for device memory, I think you should use
rte_io_mb() instead of rte_mb(). This will generate correct result. rte_wmb()
is used for system memory.
> -Original Message-
> From: Dekel Peled
> Sent: Monday, March 18, 2019 8:58 PM
> To: chao...@linux.vne
+Pradeep
> -Original Message-
> From: Thomas Monjalon
> Sent: Monday, February 18, 2019 11:47 PM
> To: David Wilder
> Cc: dev@dpdk.org; chao...@linux.vnet.ibm.com
> Subject: Re: [dpdk-stable] [PATCH v3] mem: Fix anonymous mapping on
> Power9.
>
> Hi,
>
> Long time no talk about the IBM P
_neon.c
> F: drivers/net/i40e/i40e_rxtx_vec_neon.c
> F: drivers/net/virtio/virtio_rxtx_simple_neon.c
>
> -IBM POWER
> +IBM POWER (alpha)
> M: Chao Zhu
> F: lib/librte_eal/common/arch/ppc_64/
> F: lib/librte_eal/common/include/arch/ppc_64/
> diff --git a/doc/gui
.h */
> +#define bool _Bool
> +#endif
> +
> /* Bit-field manipulation. */
> #define BITFIELD_DECLARE(bf, type, size) \
> type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \
> --
> 2.19.0
Verified, it works. Thanks!
Acked-by: Chao Zhu
-邮件原件-
发件人: Jerin Jacob
发送时间: 2018年10月7日 14:19
收件人: Chao Zhu
抄送: dev@dpdk.org; tho...@monjalon.net; gowrishanka...@linux.vnet.ibm.com;
ola.liljed...@arm.com; Jerin Jacob
主题: [dpdk-dev] [PATCH] eal/ppc64: add support for rte pause
Add support for rte_pause() implementation for ppc64
7;)
> diff --git a/lib/librte_eal/common/include/arch/ppc_64/meson.build
> b/lib/librte_eal/common/include/arch/ppc_64/meson.build
> new file mode 100644
> index 000000..00f9611768
> --- /dev/null
> +++ b/lib/librte_eal/common/include/arch/ppc_64/meson.build
> @@ -0,0 +1,16 @@
> +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Luca
> +Boccassi
> +
> +install_headers(
> + 'rte_atomic.h',
> + 'rte_byteorder.h',
> + 'rte_cpuflags.h',
> + 'rte_cycles.h',
> + 'rte_io.h',
> + 'rte_memcpy.h',
> + 'rte_pause.h',
> + 'rte_prefetch.h',
> + 'rte_rwlock.h',
> + 'rte_spinlock.h',
> + 'rte_vect.h',
> + subdir: get_option('include_subdir_arch'))
> --
> 2.18.0
Acked-by: Chao Zhu
We’ll have internal discussion and push it.
Thanks!
From: Christian Ehrhardt [mailto:christian.ehrha...@canonical.com]
Sent: 2018年8月31日 13:15
To: Chao Zhu
Cc: adrien.mazarg...@6wind.com; dev ; Gowrishankar Muthukrishnan
; Luca Boccassi ; Thomas
Monjalon
Subject: Re: [PATCH v3] ppc64: fix
ginal Message-
> From: Thomas Monjalon [mailto:tho...@monjalon.net]
> Sent: 2018年8月30日 16:37
> To: Christian Ehrhardt ; Gowrishankar
> Muthukrishnan ; Chao Zhu
> ; prad...@us.ibm.com; Alfredo Mendoza
> ; Gowrishankar Muthukrishnan
> ; Gowrishankar Muthukrishnan
&g
I think this patch is good enough to solve the confliction issue.
> -Original Message-
> From: Christian Ehrhardt [mailto:christian.ehrha...@canonical.com]
> Sent: 2018年8月30日 20:00
> To: adrien.mazarg...@6wind.com; dev ; Gowrishankar
> Muthukrishnan ; Chao Zhu
>
&
Signed-off-by: Chao Zhu
---
drivers/net/i40e/i40e_rxtx_vec_altivec.c | 35 ++
lib/librte_eal/common/arch/ppc_64/rte_cpuflags.c | 34 ++---
lib/librte_eal/common/arch/ppc_64/rte_cycles.c | 4 +++
.../common/include/arch/ppc_64/rte_atomic.h
> -Original Message-
> From: Gowrishankar [mailto:gowrishanka...@linux.vnet.ibm.com]
> Sent: 2018年2月27日 23:14
> To: dev@dpdk.org
> Cc: Chao Zhu ; sta...@dpdk.org;
> tho...@monjalon.net; Gowrishankar Muthukrishnan
>
> Subject: [PATCH] eal/ppc: fix rte_smp_mb for
> -Original Message-
> From: Lee Daly [mailto:lee.d...@intel.com]
> Sent: 2018年1月17日 22:39
> To: olivier.m...@6wind.com; remy.hor...@intel.com; or...@mellanox.com;
> bruce.richard...@intel.com; pablo.de.lara.gua...@intel.com;
> radu.nico...@intel.com; tomasz.kante...@intel.com;
> cristian
Thomas,
I think it's OK to apply this patch now. It's been verified before and it's
important for the correctness of the cycle counting on POWER.
Thank you!
> -Original Message-
> From: Thomas Monjalon [mailto:tho...@monjalon.net]
> Sent: 2018年2月7日 15
The previous patch has some misunderstanding of the the TSC frequency
counting.
I support this.
> -Original Message-
> From: Thomas Monjalon [mailto:tho...@monjalon.net]
> Sent: 2018年2月1日 8:30
> To: Gowrishankar ; Chao Zhu
>
> Cc: dev@dpdk.org
> Subject: Re: [dpdk-d
> -Original Message-
> From: Gowrishankar [mailto:gowrishanka...@linux.vnet.ibm.com]
> Sent: 2018年1月30日 16:59
> To: dev@dpdk.org
> Cc: Chao Zhu ; tho...@monjalon.net;
> Gowrishankar Muthukrishnan
> Subject: [PATCH] eal/ppc64: revert implement arch-specific TSC
From: Jonas Pfefferle1 [mailto:j...@zurich.ibm.com]
Sent: 2017年11月7日 18:16
To: Chao Zhu
Cc: 'Burakov, Anatoly' ; bruce.richard...@intel.com;
dev@dpdk.org
Subject: RE: [dpdk-dev] Huge mapping secondary process linux
"Chao Zhu" mailto:chao...@linux.vnet.ibm.com>
t; Â > Subject: Re: [dpdk-dev] Huge mapping secondary process linux
> > > > > Â >
> > > > > Â > On 27-Oct-17 1:43 PM, Jonas Pfefferle1 wrote:
> > > > > Â > >
> > > > > Â > >
> > > > > Â > > Hi @all
v;
>
> auxv_fd = open("/proc/self/auxv", O_RDONLY);
> - assert(auxv_fd);
> + assert(auxv_fd != -1);
> while (read(auxv_fd, &auxv,
> sizeof(Elf64_auxv_t)) == sizeof(Elf64_auxv_t)) {
> if (auxv.a_type == AT_HWCAP)
> --
> 2.14.1
Acked-by: Chao Zhu
> -Original Message-
> From: Gowrishankar [mailto:gowrishanka...@linux.vnet.ibm.com]
> Sent: 2017年9月21日 18:05
> To: dev@dpdk.org
> Cc: Chao Zhu ; Tomasz Kantecki
> ; Gowrishankar Muthukrishnan
>
> Subject: [PATCH v2] examples/l3fwd: optimised packet process
..@linux.vnet.ibm.com; Jerin Jacob
>
> Subject: [dpdk-dev] [PATCH 2/5] eal/ppc64: define architecture specific
rdtsc hz
>
> CC: Chao Zhu
> Signed-off-by: Jerin Jacob
> ---
> lib/librte_eal/common/include/arch/ppc_64/rte_cycles.h | 13 +
> 1 file changed, 13 i
ge-
> From: Xueming(Steven) Li [mailto:xuemi...@mellanox.com]
> Sent: 2017年8月31日 22:40
> To: Chao Zhu
> Cc: dev@dpdk.org
> Subject: multi-process shared memory on PPC
>
> Hi all,
>
> I'm testing multi-process example on PowerPC system, looks like shared
> me
Which version are you using?
> -Original Message-
> From: Xueming(Steven) Li [mailto:xuemi...@mellanox.com]
> Sent: 2017年8月31日 22:40
> To: Chao Zhu
> Cc: dev@dpdk.org
> Subject: multi-process shared memory on PPC
>
> Hi all,
>
> I'm testing mult
> -Original Message-
> From: Jerin Jacob [mailto:jerin.ja...@caviumnetworks.com]
> Sent: 2017年5月11日 18:11
> To: dev@dpdk.org
> Cc: tho...@monjalon.net; jianbo@linaro.org; vikto...@rehivetech.com;
> Jerin Jacob ; Chao Zhu
>
> Subject: [dpdk-dev] [PATCH 5
40e_rxtx.c| 30 ++-
> drivers/net/i40e/i40e_rxtx.h| 3 +-
> drivers/net/i40e/i40e_rxtx_vec_altivec.c| 22 +-
> drivers/net/i40e/i40e_rxtx_vec_neon.c | 8 +-
> drivers/net/i40e/i40e_rxtx_vec_sse.c| 14 +-
> drivers/net/i40e/rte_pmd_i40e.c
e not enough space for mmap twice in DPDK.
That's why we need to set the overcommit to expand the address space.
> -Original Message-
> From: Sergio Gonzalez Monroy [mailto:sergio.gonzalez.mon...@intel.com]
> Sent: 2017年4月6日 20:59
> To: Chao Zhu ; dev@dpdk.org
> Cc: Gow
Due to mmap implementation on IBM POWER, the secondary process memory
initialization may fail (mmap will not respect the required address hints).
This patch sets add the fixes and guides to fix this problem.
Chao Zhu (2):
eal/ppc: fix mmap for memory initialization
doc/guides: Add hugepage
This patch adds additional instructions for hugepage reservation on IBM
POWER.
Signed-off-by: Chao Zhu
---
doc/guides/linux_gsg/sys_reqs.rst | 6 ++
1 file changed, 6 insertions(+)
diff --git a/doc/guides/linux_gsg/sys_reqs.rst
b/doc/guides/linux_gsg/sys_reqs.rst
index 61222c6..3a28c9e
nr_overcommit_hugepages to expand the VA range. When
doing the initilization, users need to set both nr_hugepages and
nr_overcommit_hugepages to the same value, like 64, 128, etc.
Signed-off-by: Chao Zhu
---
lib/librte_eal/linuxapp/eal/eal_memory.c | 8
1 file changed, 8 insertions(+)
diff
Thomas,
Thanks for the reminder! I changed the mailer settings and acked again.
> -Original Message-
> From: Thomas Monjalon [mailto:thomas.monja...@6wind.com]
> Sent: 2017年3月7日 21:08
> To: Chao Zhu
> Cc: 'Gowrishankar' ; dev@dpdk.org;
> 'Anatoly Burako
> From: Gowrishankar [mailto:gowrishanka...@linux.vnet.ibm.com]
> Sent: 2017年3月6日 23:04
> To: dev@dpdk.org
> Cc: Chao Zhu ; Anatoly Burakov
> ; Thomas Monjalon
> ; Gowrishankar Muthukrishnan
>
> Subject: [PATCH v3] eal: sPAPR IOMMU support in pci probing for vfio-pc
-Original Message-
From: Gowrishankar [mailto:gowrishanka...@linux.vnet.ibm.com]
Sent: 2017年3月6日 23:04
To: dev@dpdk.org
Cc: Chao Zhu ; Anatoly Burakov
; Thomas Monjalon ;
Gowrishankar Muthukrishnan
Subject: [PATCH v3] eal: sPAPR IOMMU support in pci probing for vfio-pci in
ppc64le
From
-Original Message-
From: Gowrishankar [mailto:gowrishanka...@linux.vnet.ibm.com]
Sent: 2017年2月23日 12:39
To: dev@dpdk.org
Cc: Chao Zhu ; Helin Zhang
; Jingjing Wu ; Thomas
Monjalon ; Pradeep ;
Gowrishankar Muthukrishnan
Subject: [PATCH v4] i40e: implement vector PMD for altivec
From
onroy ; Chao Zhu
; 'Gowrishankar'
Cc: dev@dpdk.org; 'Bruce Richardson' ; 'David
Marchand'
Subject: Re: [dpdk-dev] [PATCH] eal/ppc: fix secondary process to map hugepages
in correct order
There was no follow-up on this discussion.
Please, what is the conclusion?
2016-
-Original Message-
From: Nelio Laranjeiro [mailto:nelio.laranje...@6wind.com]
Sent: 2016?11?16? 23:21
To: dev at dpdk.org
Cc: Thomas Monjalon ; Jianbo Liu
; Jerin Jacob ;
Zhigang Lu ; Liming Sun ; Chao Zhu
; Bruce Richardson ;
Konstantin Ananyev ; Adrien Mazarguil
Subject: [PATCH] eal
Thomas,
Any comments of this patch set? Are we waiting for more acks?
Thank you!
-Original Message-
From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Chao Zhu
Sent: 2016?8?17? 16:49
To: 'Gowrishankar Muthukrishnan' ;
dev at dpdk.org
Cc: 'Bruce Richardson' ;
-Original Message-
From: Gowrishankar Muthukrishnan [mailto:gowrishanka...@linux.vnet.ibm.com]
Sent: 2016?8?16? 18:28
To: dev at dpdk.org
Cc: Chao Zhu ; Bruce Richardson
; Konstantin Ananyev
; Thomas Monjalon ;
Cristian Dumitrescu ; Pradeep
Subject: [PATCH v6 0/9] enable lpm, acl and
;t do further
investigation. Can you help to double check this patch?
-Original Message-
From: Gowrishankar Muthukrishnan [mailto:gowrishanka...@linux.vnet.ibm.com]
Sent: 2016?8?12? 20:03
To: dev at dpdk.org
Cc: Chao Zhu ; Bruce Richardson
; Konstantin Ananyev
; Thomas Monjalon ;
Cri
Another comment is, comment out lcore_socket_id check will influence other
architectures. If possible, I would like to make this change to Power specific.
-Original Message-
From: gowrishankar muthukrishnan [mailto:gowrishanka...@linux.vnet.ibm.com]
Sent: 2016?8?12? 17:00
To: Chao Zhu
: Chao Zhu
Cc: dev at dpdk.org; 'Bruce Richardson' ;
'Konstantin Ananyev' ; 'Thomas Monjalon'
; 'Cristian Dumitrescu' ; 'Pradeep'
Subject: Re: [PATCH v4 3/6] ip_pipeline: fix lcore mapping for varying SMT
threads as in ppc64
On Thursday 11 Au
nka...@linux.vnet.ibm.com]
Sent: 2016?8?9? 19:14
To: Chao Zhu ; dev at dpdk.org
Cc: 'Bruce Richardson' ; 'Konstantin Ananyev'
; 'Thomas Monjalon' ; 'Cristian Dumitrescu' ; 'Pradeep'
Subject: Re: [PATCH v4 3/6] ip_pipeline: fix lcore mapping for v
Gowrishankar,
Can you give more description about this patch?
Thank you!
-Original Message-
From: Gowrishankar Muthukrishnan [mailto:gowrishanka...@linux.vnet.ibm.com]
Sent: 2016?8?6? 20:33
To: dev at dpdk.org
Cc: Chao Zhu ; Bruce Richardson
; Konstantin Ananyev
; Thomas Monjalon
m]
Sent: 2016?7?16? 15:59
To: Chao Zhu ; dev at dpdk.org
Cc: 'Bruce Richardson' ; 'Konstantin Ananyev'
; 'Thomas Monjalon'
; 'Cristian Dumitrescu'
; 'Pradeep'
Subject: Re: [PATCH v2 0/6] enable lpm, acl and other missing libraries in
ppc64le
ict-aliasing rules
[-Werror=strict-aliasing]
*indices2 = (xmm_t){((uint32_t *)&v)[0], ((uint32_t *)&v)[1],
Can you help to take a look?
-Original Message-
From: Gowrishankar [mailto:gowrishanka...@linux.vnet.ibm.com]
Sent: 2016?7?10? 15:51
To: dev at dpdk.org
Cc: Chao Zhu ; Bru
On weak memory order architecture like POWER, rte_smp_wmb/rte_smp_rmb
need to use CPU instructions, not compiler barrier. This patch fixes
this. Also, to improve performance on PPC64, use light weight sync
instruction instead of sync instruction.
Signed-off-by: Chao Zhu
---
.../common/include
Gowrishankar,
Nice patches! Do you have some function test result? I need some time to
verify the patches.
-Original Message-
From: Gowrishankar [mailto:gowrishanka...@linux.vnet.ibm.com]
Sent: 2016?7?10? 15:51
To: dev at dpdk.org
Cc: Chao Zhu ; Bruce Richardson
; Konstantin Ananyev
el.com]
Sent: 2016?6?24? 1:26
To: N?lio Laranjeiro ; Chao Zhu
Cc: dev at dpdk.org
Subject: RE: librte_meter compilation fails on IBM Power8
> -Original Message-
> From: N?lio Laranjeiro [mailto:nelio.laranjeiro at 6wind.com]
> Sent: Wednesday, June 22, 2016 1:31 PM
> To: Dumit
Nelio,
I'll check. Thanks!
-Original Message-
From: N?lio Laranjeiro [mailto:nelio.laranje...@6wind.com]
Sent: 2016?6?22? 20:31
To: Cristian Dumitrescu ; Chao Zhu
Cc: dev at dpdk.org
Subject: librte_meter compilation fails on IBM Power8
Hi Cristian, Chao,
I have encounte
This patch defines the target and arch value of objcopy program for
IBM POWER PPC64 little endian architecture. This is a fix of the
original patch proposed by Jan Viktorin .
Signed-off-by: Chao Zhu
---
mk/arch/ppc_64/rte.vars.mk |5 +
1 files changed, 5 insertions(+), 0 deletions
?20? 20:11
To: Chao Zhu ; dev at dpdk.org
Cc: david.marchand at 6wind.com; yuanhan.liu at linux.intel.com; huawei.xie at
intel.
com
Subject: Re: [PATCH v2 6/7] virtio: fix pci accesses for ppc64 in legacy
mode
Hi Chao,
On 05/19/2016 11:13 AM, Chao Zhu wrote:
> Olivier,
>
> Thanks for th
om: Sergio Gonzalez Monroy [mailto:sergio.gonzalez.mon...@intel.com]
Sent: 2016?5?20? 16:01
To: Chao Zhu ; 'Bruce Richardson'
Cc: 'Gowrishankar' ; dev at dpdk.org;
'David Marchand'
Subject: Re: [dpdk-dev] [PATCH] eal/ppc: fix secondary process to map hugepages
in
s to lower address. Here, both the
> physical
> 1318 * address and virtual address are in descending
order
> */
>
> From looking at the code, for ppc64 we do qsort in reverse order and
> thereafter everything looks to be is done to account for that reverse
> sorting.
&g
Olivier,
Thanks for the patches!
Just one comment:
POWER8 machine only supports little endian OS on bare metal. In VM guest, it
can support both little endian and big endian OS. Did you try to run it on
both host (little endian) and guest (big endian and little endian)?
-Original Message
Thomas,
Seems I didn't get the messages from David. Anyway, I sent out an updated
patch.
Thanks for reminder!
-Original Message-
From: Thomas Monjalon [mailto:thomas.monja...@6wind.com]
Sent: 2016?3?30? 18:53
To: Chao Zhu
Cc: dev at dpdk.org; David Marchand ; Richardson,
Bruce ;
. rte_prefetch0 function is
defined
to load one cache line, which means TH=0 is suited here.
Signed-off-by: Chao Zhu
---
.../common/include/arch/ppc_64/rte_prefetch.h |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/lib/librte_eal/common/include/arch/ppc_64
removes the constraint.
Signed-off-by: Chao Zhu
---
config/defconfig_ppc_64-power8-linuxapp-gcc |2 ++
lib/librte_eal/common/eal_common_options.c |3 +--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc
b/config/defconfig_ppc_64
This patch set fixes CPU/memory parameters and correct wrong prefetch settings
for IBM POWER8.
Changes in v2:
1. Move the parameter configuration to POWER specific configuration file
2. Remove the memeory channel number constraint instead of adding additional
configuration flag.
Chao Zhu (2
. rte_prefetch0 function is
defined
to load one cache line, which means TH=0 is suited here.
Signed-off-by: Chao Zhu
---
.../common/include/arch/ppc_64/rte_prefetch.h |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/lib/librte_eal/common/include/arch/ppc_64
.
2. Currently, the max number of memory channels are hardcoded to 4. However,
on a POWER8 machine, the max number of memory channels are 8. To fix this,
CONFIG_RTE_MAX_NCHANNELS is added to do the configuration.
Signed-off-by: Chao Zhu
---
config/common_base |3
This patch set fixes CPU/memory parameters and correct wrong prefetch settings
for IBM POWER8.
Chao Zhu (2):
Fix CPU and memory parameters on IBM POWER8
Fix prefetch instruction on IBM POWER8
config/common_base |3 ++-
lib/librte_eal/common
known type name
?rte_hash_cmp_eq_t?
void rte_hash_set_cmp_func(struct rte_hash *h, rte_hash_cmp_eq_t func);
Signed-off-by: Chao Zhu
---
lib/librte_hash/rte_hash.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/lib/librte_hash/rte_hash.h b/lib/librte_hash/rte_hash.h
index 6494ade.
Jerin,
Both stdio.h and stddef.h works on POWER. To make it work on ARM, I'll
use stddef.h and submit another patch.
Thanks!
On 2015/12/8 17:10, Jerin Jacob wrote:
> On Tue, Dec 08, 2015 at 04:28:52PM +0800, Chao Zhu wrote:
>> This patch fixes the compile errors caused by lack
This patch fixes the compile errors caused by lacking of "size_t" definition in
rte_hash.h.
Signed-off-by: Chao Zhu
---
lib/librte_hash/rte_hash.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/lib/librte_hash/rte_hash.h b/lib/librte_hash/rte_hash.h
ind
The fm10k vector driver is specific for x86 platform which can't compile
on IBM POWER for lacking of tmmintrin.h header file. This patch turns
off fm10k driver compilation on IBM POWER to prevent compile issue.
Signed-off-by: Chao Zhu
---
config/defconfig_ppc_64-power8-linuxapp-gcc |1
David,
Let me take a look.
On 2015/9/16 16:09, David Marchand wrote:
> Hello Chao,
>
> On Wed, Sep 16, 2015 at 4:02 AM, Chao Zhu <mailto:chaozhu at linux.vnet.ibm.com>> wrote:
>
> Actually, without this change, DPDK can't work properly on PPC64
> litt
_NUMA_NODES can
fix this. That why I invoke this patch.
On 2015/9/15 17:01, Bruce Richardson wrote:
> On Tue, Sep 15, 2015 at 03:46:49PM +0800, Chao Zhu wrote:
>> Any response of this patch?
> Looks ok to me - pretty trivial change.
>
> /Bruce
>> Forwarded Message ---
Any response of this patch?
Forwarded Message
Subject:[dpdk-dev] [PATCH] PPC: Fix NUMA node numbering on IBM POWER8
LE machine
Date: Fri, 14 Aug 2015 20:19:48 +0800
From: Chao Zhu
To: dev at dpdk.org
When Linux is running on bare metal, it gets the raw
work on POWER8 bare metal little endian machine.
Signed-off-by: Chao Zhu
---
config/common_linuxapp |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/config/common_linuxapp b/config/common_linuxapp
index 0de43d5..82a027e 100644
--- a/config/common_linuxapp
+++ b/config
Acked-by: Chao Zhu
On 2015/8/5 17:13, Thomas Monjalon wrote:
> Byte ordering macros were used without including the needed header.
>
> Fixes: ce10b21bf624 ("eal/ppc: fix cpu cycle count for little endian")
>
> Signed-off-by: Thomas Monjalon
> ---
> lib/librte
On 2015/8/3 17:06, Thomas Monjalon wrote:
> 2015-08-03 14:31, Chao Zhu:
>> The rte_cpu_to_le_32 function can't be used to define const variables
>> because it has different implementation on big endian platforms. If
>> doing so, it will cause 'initializer ele
Got it. Thanks!
On 2015/8/3 16:53, Thomas Monjalon wrote:
> 2015-08-03 14:31, Chao Zhu:
>> The using of rte_cpu_to_le_32() in pre-compile macros will cause error
>> 'initializer element is not constant' on big endian platforms. This patch
>> fixes the co
On IBM POWER8 PPC64 little endian architecture, the definition of tsc
union will be different. This patch fix this to enable the right output
from rte_rdtsc().
Signed-off-by: Chao Zhu
---
.../common/include/arch/ppc_64/rte_cycles.h|5 +
1 files changed, 5 insertions(+), 0
This patch add the definiton of tsc union for POWER8 PPC64 little endian
architecture.
Chao Zhu (1):
PPC64: add cpu cycle support to IBM POWER8 PPC64LE
.../common/include/arch/ppc_64/rte_cycles.h|5 +
1 files changed, 5 insertions(+), 0 deletions(-)
The rte_cpu_to_le_32 function can't be used to define const variables
because it has different implementation on big endian platforms. If
doing so, it will cause 'initializer element is not constant' compiling
error. This patch fixes this problem.
Signed-off-by: Chao Zhu
---
dr
The using of rte_cpu_to_le_32() in pre-compile macros will cause error
'initializer element is not constant' on big endian platforms. This patch
fixes the compilation error of fm10k driver.
Chao Zhu (1):
fm10k: fix the compilation on big endian platforms
drivers/net/fm10k/base/f
Confirmed. It can compile on Power8 Big Endian.
Thank you!
On 2015/8/3 10:39, Chao Zhu wrote:
>
> Really sorry for the delay.
> Originally, I thought the email was to asking the ABI checking tools
> on Power which I'm not so familiar with. So this took me some time to
>
Really sorry for the delay.
Originally, I thought the email was to asking the ABI checking tools on
Power which I'm not so familiar with. So this took me some time to find
solution. For Power little endian, the build is OK. I'll give feedback
when I tried Big endian compilation.
On 2015/7/31
Acked-by: Chao Zhu
On 2015/7/17 15:25, Zhe Tao wrote:
> Signed-off-by: Zhe Tao
> ---
> PATCH v3: Edit the subject make it more clear
>
> PATCH v2: Edit the comments make it more clear
>
> PATCH v1: Add the endian conversion for registers operations.
>
> drivers/net
Signed-off-by: Chao Zhu
---
MAINTAINERS |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 54f0973..8fe52c5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -105,7 +105,8 @@ F: app/test/test_mp_secondary.c
F: examples/multi_process/
F: doc
This patch added IBM ppc_64 descriptions, including architecture
support, compiling requirements on Linux.
Signed-off-by: Chao Zhu
---
doc/guides/linux_gsg/build_dpdk.rst |4 +-
doc/guides/linux_gsg/quick_start.rst | 40 +
doc/guides/linux_gsg/sys_reqs.rst
This patch added prequirements, compiling options and some IBM Power related
descriptions to Linux guides.
Chao Zhu (1):
doc: Add IBM Power description to linux guides
doc/guides/linux_gsg/build_dpdk.rst |4 +-
doc/guides/linux_gsg/quick_start.rst | 40
> On Thu, Dec 04, 2014 at 12:59:31PM +0100, Thomas Monjalon wrote:
>>>>>>> Because of different cache line size, the alignment of struct
>>>>>>> rte_kni_mbuf in rte_kni_common.h doesn't work on IBM Power. This patch
>>>>>>> changed f
gepage_sz == RTE_PGSIZE_1G) {
> hugepg_tbl[i].final_va = hugepg_tbl[i].orig_va;
> hugepg_tbl[i].orig_va = NULL;
> continue;
> @@ -422,11 +421,10 @@ remap_all_hugepages(struct hugepage_file *hugepg_tbl,
> struct hugepage_info *hpi)
> while (i < hpi->num_pages[0]) {
>
> #ifndef RTE_ARCH_64
> - /* for 32-bit systems, don't remap 1G pages and 16G pages,
> + /* for 32-bit systems, don't remap 1G pages(16G not defined,
>* just reuse original map address as final map address.
>*/
> - if ((hugepage_sz == RTE_PGSIZE_1G)
> - || (hugepage_sz == RTE_PGSIZE_16G)) {
> + if (hugepage_sz == RTE_PGSIZE_1G) {
> hugepg_tbl[i].final_va = hugepg_tbl[i].orig_va;
> hugepg_tbl[i].orig_va = NULL;
> i++;
This patch works on IBM PPC64.
Acked-by: Chao Zhu
Michael,
I'm looking at it. I'll give you feedback soon.
On 2014/12/5 14:56, Qiu, Michael wrote:
> Hi Chao
>
> Would you please take a look at this patch?
>
> It's solved issue introduce by Power Arch support patch.
>
> Your comments are very precious :)
>
> Thanks,
> Michael
> On 12/5/2014 2:03
Because of different cache line size, the alignment of struct
rte_kni_mbuf in rte_kni_common.h doesn't work on IBM Power. This patch
changed from 64 to RTE_CACHE_LINE_SIZE micro to do the alignment.
Signed-off-by: Chao Zhu
---
.../linuxapp/eal/include/exec-env/rte_kni_common.h |7 +
This patch solves the KNI compiling problem on IBM Power by using
RTE_CACHE_LINE_SIZE
micro.
Chao Zhu (1):
Fix KNI compiling issue on IBM Power
.../linuxapp/eal/include/exec-env/rte_kni_common.h |7 +--
1 files changed, 5 insertions(+), 2 deletions(-)
tter way to do the detection, I think this patch
is good enough.
Acked-by: Chao Zhu
/23/2014 9:22 PM, Chao Zhu wrote:
>> This patch adds architecture specific byte order operations for IBM Power
>> architecture. Power architecture support both big endian and little
>> endian. This patch also adds a RTE_ARCH_BIG_ENDIAN micro.
>>
>> Signed-off-by: Chao Zh
Bruce,
Good point! I'll update the current patches.
Thanks for your suggestions!
On 2014/11/25 16:44, Bruce Richardson wrote:
> On Tue, Nov 25, 2014 at 11:51:13AM +0800, Chao Zhu wrote:
>> Neil,
>> Current Power related patches are not a full functional one. Some of the
This patch fixes compiling problems on IBM Power architecture and turn
on the test-pmd compiling option in configuration file. Actually, this
is an big endian compiling fix.
Signed-off-by: Chao Zhu
---
app/test-pmd/config.c | 39 +--
1 files changed, 25
Curent implementation in test_memzone.c has bugs in finding the
second smallest memory segment. It's the last smallest memory segment,
but it's not the second smallest memory segment. This bug may cause test
failure in some cases. This patch fixes this bug.
Signed-off-by: Chao Zhu
---
systems.
Signed-off-by: Chao Zhu
---
config/defconfig_ppc_64-power8-linuxapp-gcc |1 +
config/defconfig_x86_64-native-linuxapp-clang |1 +
config/defconfig_x86_64-native-linuxapp-gcc |1 +
config/defconfig_x86_64-native-linuxapp-icc |1 +
lib/librte_eal/linuxapp/eal/eal_memory.c
IBM Power architecture has different huge page sizes (16MB, 16GB) than
x86.This patch defines RTE_PGSIZE_16M and RTE_PGSIZE_16G in the
rte_page_sizes enum variable and adds huge page size support of DPDK
for IBM Power architecture.
Signed-off-by: Chao Zhu
---
app/test/test_memzone.c
IBM Power architecture has different cache line size (128 bytes) than
x86 (64 bytes). This patch defines CACHE_LINE_SIZE to 128 bytes to
override the default value 64 bytes to support IBM Power Architecture.
Signed-off-by: Chao Zhu
---
app/test/test_malloc.c |8
mk/arch/ppc_64
ff-by: Chao Zhu
---
lib/librte_eal/linuxapp/eal/eal.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/lib/librte_eal/linuxapp/eal/eal.c
b/lib/librte_eal/linuxapp/eal/eal.c
index 7a1d087..8c0223f 100644
--- a/lib/librte_eal/linuxapp/eal/eal.c
+++ b/lib/librte_eal/lin
IBM Power processor doesn't have CPU flag hardware registers. This patch
uses aux vector software register to get CPU flags and add CPU flag
checking support for IBM Power architecture.
Signed-off-by: Chao Zhu
---
app/test/test_cpuflags.c | 35
.../c
The SSE based memory copy in DPDK only support x86. This patch adds
altivec based memory copy functions for IBM Power architecture. This
patch includes altivec.h which requires GCC version>= 4.8.
Signed-off-by: Chao Zhu
---
.../common/include/arch/ppc_64/rte_memcpy.h|
This patch adds spinlock operations for IBM Power architecture.
Signed-off-by: Chao Zhu
---
.../common/include/arch/ppc_64/rte_spinlock.h | 73
1 files changed, 73 insertions(+), 0 deletions(-)
create mode 100644 lib/librte_eal/common/include/arch/ppc_64
This patch add architecture specific prefetch operations for IBM Power
architecture.
Signed-off-by: Chao Zhu
---
.../common/include/arch/ppc_64/rte_prefetch.h | 61
1 files changed, 61 insertions(+), 0 deletions(-)
create mode 100644 lib/librte_eal/common/include
IBM Power architecture doesn't have TSC register to get CPU cycles. This
patch implements the time base register read instead of TSC register of
x86 on IBM Power architecture.
Signed-off-by: Chao Zhu
---
.../common/include/arch/ppc_64/rte_cycles.h| 88
1
1 - 100 of 181 matches
Mail list logo
