Since I was around back in the Intel Tiano days and I've worked on all the PI
specs I can share the history.
The reset vector is a hardware thing. It is usually at the top or bottom of the
address space. For x86 it is at the TOP of the ROM and that is why the FV has a
VoluteTop file GUID that
Reviewed-by: Michael Kubacki
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Nate
> DeSimone
> Sent: Wednesday, October 2, 2019 12:41 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Kubacki, Michael A
> ; Jeremy Soller
> Subject: [edk2-devel] [edk2-platforms] [PATCH
Although it is just a comment, the PcdFlashFvFspTOffset value should be
0xFFF7A000 instead of 0xFFF7C000.
> -Original Message-
> From: Desimone, Nathaniel L
> Sent: Wednesday, October 2, 2019 12:38 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Kubacki, Michael A
> ; Jeremy Soller
Please change MmioRead8 () to PciSegmentRead8 () since the address is derived
from PCI_SEGMENT_LIB_ADDRESS ().
> -Original Message-
> From: Desimone, Nathaniel L
> Sent: Wednesday, October 2, 2019 12:36 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Kubacki, Michael A
> ; Chaganty,
In platforms built for boot media other than SPI flash there has been a
compelling
need for silicon and platform code to be aware of the firmware boot media but
apart from the UEFI variable driver (which is a special case being addressed
here -
> -Original Message-
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Thursday, October 3, 2019 12:35 AM
> To: devel@edk2.groups.io; af...@apple.com
> Cc: Chang, Abner (HPS SW/FW Technologist) ;
> Philippe Mathieu-Daudé ; Mike Kinney
> ;
I am not sure if there is a silicon scope around the FirmwareBootMediaLib. Have
we considered adding this interface to MdePkg, instead?
-Original Message-
From: Kubacki, Michael A
Sent: Monday, September 30, 2019 6:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Dong, Eric
;
On Thu, Sep 19, 2019 at 11:51:26AM +0800, Gilbert Chen wrote:
> SiFive RISC-V U500 Platform Boot Manager library.
First of all, let me say that I think before upstreaming to master,
you ought to look into merging PlatformBootManagerLibs for all Risc-V
platforms. Like we have for *most*
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Hi Michael,
I have made ClevoOpenBoardPkg inactive. It is not longer an option when adding
a new bug.
Mike
From: Kubacki, Michael A
Sent: Tuesday, October 1, 2019 3:29 PM
To: 'devel@edk2.groups.io'
Cc: Kinney, Michael D ; Sinha, Ankit
; Desimone, Nathaniel L
Subject: [edk2-platforms]
Reviewed-by: Jeremy Soller
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On Thu, Sep 19, 2019 at 11:51:25AM +0800, Gilbert Chen wrote:
> The initial header file commit for SiFive U5-MC Coreplex and U500 Core
> Local interrupt definitions.
There is a generic issue here, and not just with this patch:
It is being added *after* the U500 platform, which depends on this.
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On Thu, Sep 19, 2019 at 11:51:24AM +0800, Gilbert Chen wrote:
> The initial version of SiFive U500 platform package.
>
> Signed-off-by: Gilbert Chen
> ---
> Platform/RiscV/SiFive/U500Pkg/Readme.md| 62 +++
> Platform/RiscV/SiFive/U500Pkg/U500.dec | 34 ++
>
On Thu, Sep 19, 2019 at 11:51:23AM +0800, Gilbert Chen wrote:
> Common RISC-V SEC module for RISC-V platforms.
If this is common to RISC-V platforms, this really should live in
edk2/RiscVPkg.
> Signed-off-by: Gilbert Chen
> ---
> Platform/RiscV/Universal/Sec/Riscv64/SecEntry.S | 438
Reviewed-by: Nate DeSimone
-Original Message-
From: Kubacki, Michael A
Sent: Tuesday, October 1, 2019 5:38 PM
To: devel@edk2.groups.io
Cc: Wei, David Y ; Agyeman, Prince
; Desimone, Nathaniel L
Subject: [edk2-platforms][PATCH V1 1/1] Readme.md: Add a reference to
SimicsOpenBoardPkg
Reviewed-by: Sai Chaganty
-Original Message-
From: Desimone, Nathaniel L
Sent: Wednesday, October 02, 2019 12:36 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Kubacki, Michael A
; Chaganty, Rangasai V
Subject: [edk2-platforms] [PATCH V1] KabylakeSiliconPkg: Logic Error in EISS
bit
On 10/2/19 10:26 AM, Laszlo Ersek wrote:
> On 10/02/19 17:15, Laszlo Ersek wrote:
>> Adding Phil.
>>
>> I'm looking at this patch only because one thing caught my attention in
>> the previous one, "OvmfPkg: Add support for SEV-ES AP reset vector
>> re-directing":
>>
>> On 09/19/19 21:53, Lendacky,
On 10/2/19 9:54 AM, Laszlo Ersek wrote:
> On 09/19/19 21:53, Lendacky, Thomas wrote:
>> From: Tom Lendacky
>>
>> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>>
>> A hypervisor is not allowed to update an SEV-ES guests register state,
>> so when booting an SEV-ES guest AP, the
On Thu, Sep 19, 2019 at 11:51:22AM +0800, Gilbert Chen wrote:
> FirmwareContextProcessorSpecificLib
> - Common library to consume EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
> and build up processor specific data HOB.
>
> RealTimClockLibNull
> - NULL instance of Real Time Clock library.
>
>
On Thu, Sep 19, 2019 at 11:51:21AM +0800, Gilbert Chen wrote:
> FirmwareContextProcessorSpecificLib.h
> - The difinitions of Firmware Context EDK2 implementaion based on
> RISC-V OpenSBI.
Typos:
difinitions ->
definitions
implementaion ->
implementation
>
> Signed-off-by: Gilbert Chen
> ---
>
On Wed, Oct 02, 2019 at 11:27:16AM -0500, Andrew Fish via Groups.Io wrote:
>
>
> > On Oct 2, 2019, at 11:14 AM, Abner Chang wrote:
> >
> > Thanks Leif, let me check with maintainers.
> >
> > Hi Mike and Liming,
> > How do you think about to use IoLibArm as the I/O lib instance for RISC-V
> >
> On Oct 2, 2019, at 11:14 AM, Abner Chang wrote:
>
> Thanks Leif, let me check with maintainers.
>
> Hi Mike and Liming,
> How do you think about to use IoLibArm as the I/O lib instance for RISC-V
> arch? I personally don't like to use IoLibArm.c in [Source.RISCV64] section,
> instead I
On 10/2/19 7:30 AM, Laszlo Ersek via Groups.Io wrote:
> On 10/02/19 14:24, Laszlo Ersek wrote:
>> On 09/19/19 21:52, Lendacky, Thomas wrote:
>>> From: Tom Lendacky
>>>
>>> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>>>
>>> The SEC phase of OVMF will need access to the
Thanks Leif, let me check with maintainers.
Hi Mike and Liming,
How do you think about to use IoLibArm as the I/O lib instance for RISC-V arch?
I personally don't like to use IoLibArm.c in [Source.RISCV64] section, instead
I would like to use IoLibRiscV.c which conform with current source file
On 10/2/19 7:05 AM, Laszlo Ersek via Groups.Io wrote:
> On 09/19/19 21:52, Lendacky, Thomas wrote:
>> From: Tom Lendacky
>>
>> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>>
>> The SEV support will clear the C-bit from non-RAM areas. The early GDT
>> lives in a non-RAM area, so when
On 10/2/19 6:51 AM, Laszlo Ersek wrote:
> A few more comments:
>
> On 09/19/19 21:52, Lendacky, Thomas wrote:
>> From: Tom Lendacky
>>
>> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>>
>> A per-CPU implementation for holding values specific to a CPU when
>> running as an SEV-ES
On 10/02/19 16:43, Lendacky, Thomas wrote:
> On 10/2/19 5:23 AM, Laszlo Ersek wrote:
>> On 09/19/19 21:52, Lendacky, Thomas wrote:
>>> @@ -38,6 +44,34 @@ AmdSevEsInitialize (
>>>
>>>PcdStatus = PcdSetBoolS (PcdSevEsActive, 1);
>>>ASSERT_RETURN_ERROR (PcdStatus);
>>> +
>>> + //
>>> +
On 10/02/19 17:15, Laszlo Ersek wrote:
> Adding Phil.
>
> I'm looking at this patch only because one thing caught my attention in
> the previous one, "OvmfPkg: Add support for SEV-ES AP reset vector
> re-directing":
>
> On 09/19/19 21:53, Lendacky, Thomas wrote:
>> From: Tom Lendacky
>>
>> BZ:
Adding Phil.
I'm looking at this patch only because one thing caught my attention in
the previous one, "OvmfPkg: Add support for SEV-ES AP reset vector
re-directing":
On 09/19/19 21:53, Lendacky, Thomas wrote:
> From: Tom Lendacky
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
Jason,
The only time the HardwareInstance is optional (and set to 0) is if the system
can guarantee that there is at most one instance of the device in the system.
This can only be guaranteed for an integrated device. Any devices that an end
user can add/remove from the system through slots
On 09/19/19 21:53, Lendacky, Thomas wrote:
> From: Tom Lendacky
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> A hypervisor is not allowed to update an SEV-ES guests register state,
> so when booting an SEV-ES guest AP, the hypervisor is not allowed to
> set the RIP to the guest
On 10/2/19 5:23 AM, Laszlo Ersek wrote:
> After the discussion elsewhere in this patch thread, which related to
> commit messages, and patch order in the series, I can make a few coding
> style comments on the patch. (No change to functionality.)
>
> On 09/19/19 21:52, Lendacky, Thomas wrote:
>>
On 09/20/19 15:16, Lendacky, Thomas wrote:
> From: Tom Lendacky
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> After having transitioned from UEFI to the OS, the OS will need to boot
> the APs. For an SEV-ES guest, the APs will have been parked by UEFI using
> GHCB pages
On 09/19/19 21:52, Lendacky, Thomas wrote:
> From: Tom Lendacky
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> Currently, the OVMF code relies on the hypervisor to enable the cache
> support on the processor in order to improve the boot speed. However,
> with SEV-ES, the
On 10/02/19 14:24, Laszlo Ersek wrote:
> On 09/19/19 21:52, Lendacky, Thomas wrote:
>> From: Tom Lendacky
>>
>> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>>
>> The SEC phase of OVMF will need access to the MemEncryptSevLib library,
>> so make the library available during SEC.
>>
>>
On 09/19/19 21:52, Lendacky, Thomas wrote:
> From: Tom Lendacky
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> The SEC phase of OVMF will need access to the MemEncryptSevLib library,
> so make the library available during SEC.
>
> Cc: Jordan Justen
> Cc: Laszlo Ersek
> Cc:
On 09/19/19 21:52, Lendacky, Thomas wrote:
> From: Tom Lendacky
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> The SEV support will clear the C-bit from non-RAM areas. The early GDT
> lives in a non-RAM area, so when an exception occurs (like a #VC) the GDT
> will be read as
A few more comments:
On 09/19/19 21:52, Lendacky, Thomas wrote:
> From: Tom Lendacky
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> A per-CPU implementation for holding values specific to a CPU when
> running as an SEV-ES guest, specifically to hold the Debug Register
> value.
After the discussion elsewhere in this patch thread, which related to
commit messages, and patch order in the series, I can make a few coding
style comments on the patch. (No change to functionality.)
On 09/19/19 21:52, Lendacky, Thomas wrote:
> From: Tom Lendacky
>
> BZ:
On Wed, Oct 02, 2019 at 01:30:12AM +, Chang, Abner (HPS SW/FW Technologist)
wrote:
> > There should be exactly one variant of IoLib.c. Well, these days we need a
> > separate one for ARM/AARCH64 under hw virtualization.
> >
> > IoLibArm, IoLibEbc and IoLibRiscV have *exactly* the same
On Thu, Sep 19, 2019 at 11:51:20AM +0800, Gilbert Chen wrote:
> Initial version of RISC-V platform package which provides the common
> libraries, drivers, PCD and etc. for RISC-V platform development.
>
> Signed-off-by: Gilbert Chen
> ---
> Platform/RiscV/Readme.md | 89
>
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ORGANIZER;CN=Stephano Cetola:mailto:stephano.cet...@linux.intel.com
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The GalagoPro3 platform in KabylakeOpenBoardPkg is using the
instance of PlatformSecLib in MinPlatformPkg instead of the
instance in KabylakeOpenBoardPkg. The version in MinPlatformPkg
does not support FSP 2.1 Dispatch Mode, whearas the version in
KabylakeOpenBoardPkg does.
Cc: Chasel Chiu
Cc:
Resize the flash map for the GalagoPro3 platform to provide
enough space to accommodate a debug build of FSP-T.
Cc: Chasel Chiu
Cc: Michael Kubacki
Cc: Jeremy Soller
Signed-off-by: Nate DeSimone
---
.../GalagoPro3/Include/Fdf/FlashMapInclude.fdf | 6 +++---
1 file changed, 3
Current ASSERT logic checks that the EISS bit is still
set after we clear it. This is incorrect, it should be
checking that that the EISS bit is clear after we clear it.
Cc: Chasel Chiu
Cc: Michael Kubacki
Cc: Sai Chaganty
Signed-off-by: Nate DeSimone
---
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