Hi Sunil, V2 sent.
Thanks for the review.
Abner
From: Sunil V L
Sent: Friday, January 21, 2022 10:53 PM
To: devel@edk2.groups.io ; Chang, Abner (HPS SW/FW
Technologist)
Cc: Schaefer, Daniel (ROM Janitor)
Subject: Re: [edk2-devel] [edk2-platforms][PATCH 11/14] R
Fix the build error caused by the spelling correction.
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
.../SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Platform/SiFive/U5SeriesPkg/Library/PeiCo
Fix the build error caused by the spelling correction.
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLi
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
.../Include/IndustryStandard/RiscV.h | 156 ++---
.../Include/IndustryStandard/RiscVOpensbi.h | 28 +-
.../Include/Library/MachineModeTimerLib.h | 4 +-
.../Include/Library/RiscVCpuLib.h | 76 ++-
..
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 1 -
1 file changed, 1 deletion(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
index 045fc55212..59634f44
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec| 4 ++--
.../RiscVFirmwareContextSbiLib.inf | 6 +++---
.../RiscVFirmwareContextSscratchLib.inf | 4 ++--
.../Include/Library/RiscVEdk2SbiLib.h
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 2 ++
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 4 ++--
.../RiscVFirmwareContextSbiLib.inf| 2 +-
.../Include/Library/MachineModeTimerLib.h | 15
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
.../Library/Edk2OpensbiPlatformWrapperLib.h | 2 +-
.../FirmwareContextProcessorSpecificLib.h | 17 +-
.../Include/Library/PlatformSecPpiLib.h | 2 +-
.../Library/RiscVPlatformTempMemoryInitLib.h | 18 +-
.../Pl
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
index f3217e4a05..b45f48fd
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
.../PlatformPkg/Universal/Sec/Riscv64/SecEntry.S | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
b/Platform/RISC-V/PlatformPkg/Univ
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
.../RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf | 1 -
1 file changed, 1 deletion(-)
diff --git
a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
b/Platform/RISC-V/PlatformPkg/Universal/Pe
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 1 -
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 4 +-
.../FirmwareContextProcessorSpecificLib.inf | 7 +-
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 2 +-
.../PeiCore
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 4 ++--
.../FirmwareContextProcessorSpecificLib.inf| 2 +-
.../PlatformPkg/Universal/FdtPeim/FdtPeim.inf | 2 +-
.../Library/FirmwareContextProcessorSpecificLib.
Fix the build error caused by the dependency with SiFive silicon code.
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
.../Universal/Pei/PlatformPei/PlatformPei.inf | 7 +--
.../Universal/Pei/PlatformPei/Platform.h| 13 -
.../Universal/Pei/Pl
Add FdtLib to DSC file.
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 1 +
1 file changed, 1 insertion(+)
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
This patch set addresses edk2 Core CI on RISC-V ProcessorPkg
and PlatformPkg.
V2: Address comments to V1.
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
Abner Chang (14):
RiscVProcessorPkg: Fix build fail on RiscVProcessorPkg package
PlatformPkg/PlatformPei: Fix the build e
> -Original Message-
> From: Sunil V L
> Sent: Friday, January 21, 2022 10:48 PM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
>
> Cc: Schaefer, Daniel (ROM Janitor)
> Subject: Re: [edk2-devel] [edk2-platforms][PATCH 09/14] RISC-
> V/ProcessorPkg: Address Core CI E
Hi Lisa,
Thank you for contributing this. Please include me on functionality
related to PRM.
I was using the PRM_EXPORT_API macro
(https://github.com/tianocore/edk2-staging/blob/9da8abf66505d8ff636aaecc429a5237ce226650/PrmPkg/Include/Prm.h#L17)
to support this on MS toolchain.
It looks lik
The series has been pushed as 3de8b92~..8eb3b2f
-Original Message-
From: Jiang, Guomin
Sent: Thursday, January 20, 2022 4:57 PM
To: devel@edk2.groups.io
Cc: GuoMinJ ; Desimone, Nathaniel L
; Jiang, Guomin
Subject: [ed2-platforms][PATCH 1/2] Platform/Intel/SimicsOpenBoardPkg: Remove
al
Reviewed-by: Nate DeSimone
-Original Message-
From: Jiang, Guomin
Sent: Thursday, January 20, 2022 4:57 PM
To: devel@edk2.groups.io
Cc: GuoMinJ ; Desimone, Nathaniel L
; Sun, Zailiang ; Qian,
Yi ; Jiang, Guomin
Subject: [ed2-platforms][PATCH 2/2] Platform/Intel: Remove All UGA Suppor
Reviewed-by: Nate DeSimone
-Original Message-
From: Jiang, Guomin
Sent: Thursday, January 20, 2022 4:57 PM
To: devel@edk2.groups.io
Cc: GuoMinJ ; Desimone, Nathaniel L
; Jiang, Guomin
Subject: [ed2-platforms][PATCH 1/2] Platform/Intel/SimicsOpenBoardPkg: Remove
all UGA support
From:
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3811
Remove ASSERT() statements that are triggered if a platform provides
an override of PCI ROM attached to a PCI Controller. The PCI Platform
Protocol allows the platform to provide a PCI ROM image for a PCI
Controller. This works for PCI Con
For the series...
Reviewed-by: Nate DeSimone
-Original Message-
From: Oram, Isaac W
Sent: Wednesday, January 19, 2022 5:14 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Gao, Liming
; Dong, Eric ; Tan, Ming
; Desimone, Nathaniel L ;
Chiu, Chasel ; Bi, Dandan ; Shindo,
Miki
Pushed: https://github.com/tianocore/edk2-platforms/commit/b927644
-Original Message-
From: devel@edk2.groups.io On Behalf Of Nate DeSimone
Sent: Wednesday, January 19, 2022 3:59 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Oram, Isaac W
; Gao, Liming ; Kinney,
Michael D
Subj
Add a vendor reserved range to avoid collisions with Intel reference
board ID future use, if any.
Cc: Nate DeSimone
Cc: Chasel Chiu
Signed-off-by: Isaac Oram
---
Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.c |
3 +-
Platform/Intel/WhitleyOpenBoardPkg/Readme.md
This series adds a template for board porting and the infrastruture to support.
The WhitleyOpenBoardPkg/Readme.md documents the step by step instructions to
create a new board tip that builds.
The BoardPortTemplate contains build files and typically required Universal
Board Abstraction (UBA) module
Pushed as b2503a71a3..0b4770e1ca
-Original Message-
From: Bi, Dandan
Sent: Thursday, January 20, 2022 9:11 PM
To: Oram, Isaac W ; devel@edk2.groups.io
Cc: Gao, Liming ; Palomino Sosa, Guillermo A
Subject: RE: [edk2-devel][edk2-platforms][PATCH V1 1/1]
UserAuthFeaturePkg/PlatformPasswo
Ok Mike and Leif,
Another question regarding to the location of RISC-V Virtual package for QEMU.
What is the location and package you think RISC-V or other processor
architectures should stay with?
Thanks
Abner
From: Kinney, Michael D
Sent: Saturday, January 15,
Comments below.
Mike
> -Original Message-
> From: kra...@redhat.com
> Sent: Friday, January 21, 2022 12:31 AM
> To: Yao, Jiewen
> Cc: devel@edk2.groups.io; Kinney, Michael D ;
> Wang, Jian J ; Jiang, Guomin
> ; Pawel Polawski ; Lu, XiaoyuX
>
> Subject: Re: [edk2-devel] [PATCH 00/24]
The 64-bit integer math intrinsics need to be addressed in the intrinsic lib
for the CryptoPkg.
I would expect the X64 build to not require those and they should only be
observed for the IA32 builds.
Mike
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Gerd Hoffmann
> S
On Fri, Jan 21, 2022 at 04:48:45PM +0800, Abner Chang wrote:
> Signed-off-by: Abner Chang
> Cc: Daniel Schaefer
> Cc: Sunil V L
> ---
> .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec| 4 ++--
> .../RiscVFirmwareContextSbiLib.inf | 6 +++---
> .../RiscVFirmwareContextSscratchL
On Fri, Jan 21, 2022 at 04:48:43PM +0800, Abner Chang wrote:
> Signed-off-by: Abner Chang
> Cc: Daniel Schaefer
> Cc: Sunil V L
> ---
> .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 2 ++
> .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 4 ++--
> .../RiscVFirmwareContextSbiLib.inf
On Fri, Jan 21, 2022 at 04:48:37PM +0800, Abner Chang wrote:
> Signed-off-by: Abner Chang
> Cc: Daniel Schaefer
> Cc: Sunil V L
> ---
> .../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 1 -
> .../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 4 +-
> .../FirmwareContextProcessorSpecificLib.inf
> Why do you need the former? To figure the highest address used in PEI,
> whereas the DXE drivers use the other one?
Yes that's right.
> Usual naming convention for that case would be PeiHardwareInfoLib +
> DxeHardwareInfoLib ...
Understood, will change the naming to comply with the convention
Hi Gerd,
> Hmm, the QemuFwCfgHardwareInfoLib.inf file created by patch #2 has
> HardwareInfoPciHostBridgeLib.c + QemuFwCfgHardwareInfoLib.c too.
> I'm wondering why you add two inf files in the first place?
My idea was to provide 2 variations of the library:
- One offering no dynamic memory an
ovmf default display resolution is 800x600. This is rather small for
modern guests. qemu used 1024x768 as default for a long time and
switched the to 1280x800 recently[1] for the upcoming 7.0 release.
This patch brings ovmf in sync with the recent qemu update and likewise
switches the default to
Gerd Hoffmann (2):
OvmfPkg: change qemu default resolution to 1280x800
ArmVirtPkg: change qemu default resolution to 1280x800
ArmVirtPkg/ArmVirtQemu.dsc | 4 ++--
ArmVirtPkg/ArmVirtQemuKernel.dsc | 4 ++--
OvmfPkg/AmdSev/AmdSevX64.dsc | 4 ++--
OvmfPkg/Microvm/MicrovmX64.dsc |
ovmf default display resolution is 800x600. This is rather small for
modern guests. qemu used 1024x768 as default for a long time and
switched the to 1280x800 recently[1] for the upcoming 7.0 release.
This patch brings ovmf in sync with the recent qemu update and likewise
switches the default to
When setting mVirtualMap to NULL also set mVirtualMapMaxIndex to 0.
Without that RuntimeDriverConvertPointer() will go search the ZeroPage
for EFI_MEMORY_DESCRIPTOR entries.
In case mVirtualMapMaxIndex happens to be small small enough that'll go
unnoticed, the search will not find anything and EFI
On Fri, Jan 21, 2022 at 10:48:06AM +, Ojeda Leon, Nicolas wrote:
> Hi Gerd,
>
> > Hmm, the QemuFwCfgHardwareInfoLib.inf file created by patch #2 has
> > HardwareInfoPciHostBridgeLib.c + QemuFwCfgHardwareInfoLib.c too.
>
> > I'm wondering why you add two inf files in the first place?
>
> My
On Thu, Jan 20, 2022 at 06:10:14PM +0100, Nicolas Ojeda Leon wrote:
> Create the Hardware Info library base together with the specifics to
> describe PCI Host Bridges.
>
> The Hardware Info library is intended to be used for disclosing
> non-discoverable hardware information from the host to the g
> +++ b/OvmfPkg/Library/HardwareInfoLib/HardwareInfoLib.inf
> +[Sources]
> + HardwareInfoLib.c
> + HardwareInfoPciHostBridgeLib.c
> + QemuFwCfgHardwareInfoLib.c
> + HardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/HardwareInfoLib.inf
>
> QemuFwCfgHardwareInfoLib|OvmfPkg/Library/HardwareInf
hi,
> As an example, if the PcdPciMmio64Size is initialized to 0x8
> and the runtime calculated base address produces the value 0x8,
> the last 64-bit MMIO address a PCI host bridge may use would be
> 0xF. If one of the host-specified bridges defines a high
> memory windo
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
.../Include/IndustryStandard/RiscV.h | 156 ++---
.../Include/IndustryStandard/RiscVOpensbi.h | 28 +-
.../Include/Library/MachineModeTimerLib.h | 4 +-
.../Include/Library/RiscVCpuLib.h | 76 ++-
..
Fix the build error caused by the spelling correction.
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
.../SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Platform/SiFive/U5SeriesPkg/Library/PeiCo
Fix the build error caused by the spelling correction.
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLi
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec| 4 ++--
.../RiscVFirmwareContextSbiLib.inf | 6 +++---
.../RiscVFirmwareContextSscratchLib.inf | 4 ++--
.../Include/Library/RiscVEdk2SbiLib.h
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 1 -
1 file changed, 1 deletion(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
index 045fc55212..59634f44
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 2 ++
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 4 ++--
.../RiscVFirmwareContextSbiLib.inf| 2 +-
.../Include/Library/MachineModeTimerLib.h | 15
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
.../Library/Edk2OpensbiPlatformWrapperLib.h | 2 +-
.../FirmwareContextProcessorSpecificLib.h | 17 +-
.../Include/Library/PlatformSecPpiLib.h | 2 +-
.../Library/RiscVPlatformTempMemoryInitLib.h | 18 +-
.../Pl
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
.../RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf | 1 -
1 file changed, 1 deletion(-)
diff --git
a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
b/Platform/RISC-V/PlatformPkg/Universal/Pe
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
index f3217e4a05..b45f48fd
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
.../PlatformPkg/Universal/Sec/Riscv64/SecEntry.S | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
b/Platform/RISC-V/PlatformPkg/Univ
Fix the build error caused by the dependency with SiFive silicon code.
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
.../Universal/Pei/PlatformPei/PlatformPei.inf | 7 +--
.../Universal/Pei/PlatformPei/Platform.h| 13 -
.../Universal/Pei/Pl
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 4 ++--
.../FirmwareContextProcessorSpecificLib.inf| 2 +-
.../PlatformPkg/Universal/FdtPeim/FdtPeim.inf | 2 +-
.../Library/FirmwareContextProcessorSpecificLib.
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 1 -
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 4 +-
.../FirmwareContextProcessorSpecificLib.inf | 7 +-
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 2 +-
.../PeiCore
Add FdtLib to DSC file.
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
---
Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 1 +
1 file changed, 1 insertion(+)
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
This patch set addresses edk2 Core CI on RISC-V ProcessorPkg
and PlatformPkg.
Signed-off-by: Abner Chang
Cc: Daniel Schaefer
Cc: Sunil V L
Abner Chang (14):
RiscVProcessorPkg: Fix build fail on RiscVProcessorPkg package
PlatformPkg/PlatformPei: Fix the build error
RISC-V/PlatformPkg: Add
Reviewed-by: Jenny Huang
-Original Message-
From: Sheng, W
Sent: Tuesday, January 18, 2022 4:15 PM
To: devel@edk2.groups.io
Cc: Ni, Ray ; Chaganty, Rangasai V
; Huang, Jenny ;
Kowalewski, Robert
Subject: [PATCH v5 3/4] IntelSiliconPkg/VTd: Support VTd Abort DMA Mode
If VTd ECAP_REG.
Reviewed-by: Jenny Huang
-Original Message-
From: Sheng, W
Sent: Tuesday, January 18, 2022 4:15 PM
To: devel@edk2.groups.io
Cc: Ni, Ray ; Chaganty, Rangasai V
; Huang, Jenny ;
Kowalewski, Robert
Subject: [PATCH v5 4/4] IntelSiliconPkg/VTd: Only generate PEI DMA buffer once.
VTdInfoN
Hi,
> > > I still have a bunch of failures in CI, for some of them I'm not sure
> > > how to handle them best:
> > >
> > > (1) 32-bit builds on windows fail:
> > >
> > > INFO - OpensslLibCrypto.lib(rsa_lib.obj) : error LNK2001: unresolved
> > > external
> > > symbol __allmul
> > > INFO - Openss
On January 21, 2022 4:04 PM, Gerd Hoffmann wrote:
> > > Can we move most of the code to a (x64) page table library instead
> > > of
> > > cut+pasting like this, please?
>
> > As I explained in https://edk2.groups.io/g/devel/message/85582, there
> > has already been a same feature requirement.
> >
> > No changes in SEC and PEI.
> [Jiewen] Do you mean the Crypto consumer in PEI has no size difference? Such
> as
> https://github.com/tianocore/edk2/tree/master/SecurityPkg/Tcg/Tcg2Pei ,
> https://github.com/tianocore/edk2/tree/master/SecurityPkg/FvReportPei ,
> https://github.com/tianocore/edk2
Reviewed-by: Jenny Huang
-Original Message-
From: Sheng, W
Sent: Tuesday, January 18, 2022 4:15 PM
To: devel@edk2.groups.io
Cc: Ni, Ray ; Chaganty, Rangasai V
; Huang, Jenny ;
Kowalewski, Robert
Subject: [PATCH v5 2/4] IntelSiliconPkg/VTd: Update VTd register structs
Update VTd regi
On Wed, Jan 19, 2022 at 05:03:30PM -0600, Brijesh Singh wrote:
> This is the first of cleanup for SEV MemEncryptLib. The library uses
> the CPUID followed by the MSR read to determine whether SEV is enabled.
>
> Now that we have a workarea concept, the logic can be simplified to
> store the msr st
Hi,
> > Can we move most of the code to a (x64) page table library instead of
> > cut+pasting like this, please?
> As I explained in https://edk2.groups.io/g/devel/message/85582, there
> has already been a same feature requirement.
> https://bugzilla.tianocore.org/show_bug.cgi?id=847 . (Create
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