Reviewed-by: Ray Ni
> -Original Message-
> From: Guo, Gua
> Sent: Monday, June 27, 2022 1:03 PM
> To: Ni, Ray ; devel@edk2.groups.io
> Cc: Dong, Guo ; Lu, James
> Subject: RE: [PATCH] UefiPayloadPkg: Align Attribute value with UPL spec
>
> Yes, #2 is chosen in by the python interpreter
RD-N2-Cfg2 platform is the multichip variant of the RD-N2 platform. The
platform is based on 4xMP1 Neoverse N2 CPUs per chip, CMN-700
interconnect 6x6 mesh, multiple AXI expansion ports for I/O Coherent
PCIe, Ethernet, offload and Arm Cortex-M7 for System Control Processor
(SCP) and Manageability C
Extend the SMBIOS support for RD-N2-Cfg2 platform which is a quad-chip
variant of the RD-N2 platform. Most the SMBIOS information is shared
with the RD-N2 platform except for the number of the CPUs supported on
the RD-N2-Cfg2 platform.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/Drivers/
From: Vijayenthiran Subramaniam
The RD-N2-Cfg2 platform is a quad-chip variant of the RD-N2 platform.
Each chip has reduced core count of four Neoverse N2 CPUs when compared
to the single-chip RD-N2 platform. Enable support for the RD-N2-Cfg2
platform.
Signed-off-by: Vijayenthiran Subramaniam
S
From: Vijayenthiran Subramaniam
Add MADT, DSDT and SRAT ACPI tables that are specific for RD-N2-Cfg2
platform. The rest of the ACPI tables are reused from the shared ACPI
tables in SgiPkg.
Signed-off-by: Vijayenthiran Subramaniam
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/
From: Vijayenthiran Subramaniam
The RD-N2-Cfg2 platform is a quad-chip variant of the RD-N2 platform
but with reduced core count, that is, each instance of the RD-N2 chip
has four cores. This platform shares the same product and config ID
as the RD-N2 platform.
As a preparatory step towards addi
From: Vijayenthiran Subramaniam
Add a new PCD to define the maximum number of address bits used for
addresses within a chip. The value of this PCD can be used to derive the
maximum addressable memory region for each chip and to calculate the
address space offset of a remote chip on multi-chip pla
Update the RD-V1-MC platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gon
Update the SGI575 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondo
Update the RD-N1-Edge-X2 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierr
Update the RD-N2-Cfg1 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre G
Update the RD-N2 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondoi
Update the RD-V1 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondoi
Update the RD-E1-Edge platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre G
Update the RD-N1-Edge platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre G
Update the common ACPI tables used by all the Neoverse Reference Design
platforms to ACPI version v6.4. Significant changes introduced are
update API/macro definitions to incorporate with the extra fields
introduced in ACPI 6.4, such as SPE overflow interrupt number field to
GICC structure of MADT
Changes since V3:
- Addressed comments from Pierre Gondois
- Rebased on top of latest master branch
Changes since V2:
- Rebased on top of latest master branch
- Update PPTT table with unique cache ID across the system for different
levels of cache.
Changes since V1:
- Rebased on top of latest m
> +upld_info_hdr.Attribute |= 1 if BuildTarget == "DEBUG" else 0
I am not python expert. Above statement might be interpreted as:
1. (upld_info.hdr.Attribute |= 1) if BuildTarget == "DEBUG" else 0
2. upld_info_hdr.Attribute |= (1 if BuildTarget == "DEBUG" else 0)
Are we sure that the #2 is c
Merged via:
PR - https://github.com/tianocore/edk2/pull/3014
Commit -
https://github.com/tianocore/edk2/commit/7f4eca4cc2e01d4160ef265f477f9d098d7d33df
Best Regards,
Hao Wu
> -Original Message-
> From: Wu, Hao A
> Sent: Thursday, June 23, 2022 2:50 PM
> To: devel@edk2.groups.io; Chiu, Ia
Reviewed-by: Yuwei Chen
> -Original Message-
> From: Feng, Bob C
> Sent: Saturday, June 25, 2022 1:12 PM
> To: devel@edk2.groups.io
> Cc: Feng, Bob C ; Gao, Liming
> ; Chen, Christine
> Subject: [Patch] BaseTools: Fix the GenMake bug for .cpp source file
>
> From: "Feng, Bob C"
>
> Bu
Reviewed-by: Bob Feng
-Original Message-
From: Chen, Christine
Sent: Friday, June 24, 2022 9:25 AM
To: devel@edk2.groups.io; quic_rc...@quicinc.com; Feng, Bob C
; Gao, Liming
Subject: RE: [edk2-devel] [PATCH 1/1] BaseTools/Ecc: Fix grammar in Ecc error
message
Reviewed-by: Yuwei Che
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