Only need to include Network.dsc.inc to have all network
drivers/components be built. Otherwise, there were missing definition
that prevent them from be built for RiscVVirt platform.
Signed-off-by: Tuan Phan
---
v2:
- Rebase
OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 15 +--
1 file chan
Hi Marcin,
> -Original Message-
> From: Marcin Wojtas
> Sent: Friday, January 12, 2024 4:19 AM
> To: devel@edk2.groups.io; Narinder Dhillon
> Cc: quic_llind...@quicinc.com; marcin.s.woj...@gmail.com; Szymon Balcerak
>
> Subject: [EXT] Re: [edk2-devel] [edk2-platforms PATCH v2 7/8]
> Si
Update the RegisterBase and Clk for the Debug Serial Port (DBG2)
to route it to the IOFPGA UART1 and make the SPCR and DBG2 Serial
Ports exclusive.
Signed-off-by: Himanshu Sharma
---
Change-log:
V2:
- Reverse updating the IRQ ID for DBG2 UART.
- Update the commit message.
Platfor
> On Jan 12, 2024, at 11:04 AM, Kinney, Michael D
> wrote:
>
> Agreed. Basically every API that takes an EF_HANDLE as input calls that API
> to make sure it is a valid handle.
>
> The first question is if we get value from making sure the EFI_HANDLE is a
> member of the active set of hand
From: Thomas Barrett
The PlatformScanE820 utility function is not currently compatible
with CloudHv since it relies on the prescence of the "etc/e820"
QemuFwCfg file. Update the PlatformScanE820 to iterate through the
PVH e820 entries when running on a CloudHv guest.
Cc: Anatol Belski
Cc: Ard B
From: Thomas Barrett
Without enabling PcdUse1GPageTable, CloudHv guests are limited
to a 40-bit address space, even if the hardware supports more.
This limits the amount of RAM to 1TiB of CloudHv guests.
Cc: Anatol Belski
Cc: Ard Biesheuvel
Cc: Gerd Hoffmann
Cc: Jianyong Wu
Cc: Jiewen Yao
C
From: Thomas Barrett
In addition to initializing the PhysMemAddressWidth and
FirstNonAddress fields in PlatformInfoHob, the
PlatformAddressWidthInitialization function is responsible
for initializing the PcdPciMmio64Base and PcdPciMmio64Size
fields.
Currently, for CloudHv guests, the PcdPciMmio6
From: Ard Biesheuvel
Remove me as reviewer for ARM development platforms: I am no longer
employed by ARM and have no access to or knowledge about ARM
development/reference hardware.
Signed-off-by: Ard Biesheuvel
---
Maintainers.txt | 1 -
1 file changed, 1 deletion(-)
diff --git a/Maintainers
From: caiyuqing379
Override Sstc extension and use SBI calls itself by default for RISC-V
Sophgo SG2042 platform.
Cc: dahogn
Cc: meng-cz
Cc: USER0FISH
Cc: Sunil V L
Signed-off-by: caiyuqing379
---
Platform/Sophgo/SG2042_EVB_Board/SG2042.dsc | 1117 ++--
1 file changed, 559
This series adds support for cloud-hypervisor guests with >1TiB
of RAM to Ovmf. This bug was solved for Qemu back in 2017
https://bugzilla.redhat.com/show_bug.cgi?id=1468526. The bug is
still occuring for CloudHv guests because the PlatformScanE820
utility is not currently supported for CloudHv.
M
From: caiyuqing379
By default the Sstc feature is enabled and Sophgo SG2042 platform need
to set the PCD to disable the feature because Sstc is not supported.
Cc: dahogn
Cc: meng-cz
Cc: USER0FISH
Cc: Sunil V L
Signed-off-by: caiyuqing379
caiyuqing379 (1):
Sophgo/SG2042Pkg: Override Sstc
Hi, everyone
Sorry, there is a problem with the formatting of this series of patches and it
can't be retracted, please ignore this series and the correct series will be
sent again later.
Thanks!
Yuqing Cai
At 2024-01-12 22:16:23, caiyuqing...@163.com wrote:
>From: caiyuqing379
>
>B
Hi Liming,
Could you help to share the update for this patch solution?
Best Regards,
Zifeng
-Original Message-
From: Yang, Yuting2
Sent: Monday, December 25, 2023 3:10 PM
To: Gao, Liming
Cc: Zhang, Zifeng ; Chen, Christine
; devel@edk2.groups.io
Subject: RE: [Patch V2] BaseTools: Vfr
Currently the types of casting mismatch with TD MMIO read 1, 2 and 4
bytes, that might introduce potential issues. So fix the types as
conventional MmioRead[8|16|32] does.
Signed-off-by: Zhiquan Li
---
MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c | 6 +++---
1 file changed, 3 insertions
Currently the types of casting mismatch with TD MMIO read 1, 2 and 4
bytes, that might introduce potential issues. So fix the types as
conventional MmioRead[8|16|32] does.
Signed-off-by: Zhiquan Li
---
MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c | 6 +++---
1 file changed, 3 insertions(
This creates / adds a security file that tracks the security fixes
found in this package and can be used to find the fixes that were
applied.
Cc: Jiewen Yao
Signed-off-by: Doug Flick [MSFT]
---
SecurityPkg/SecurityFixes.yaml | 14 ++
1 file changed, 14 insertions(+)
diff --git a/S
This commit contains the patch files and tests for DxeTpmMeasureBootLib
CVE 2022-36764.
Cc: Jiewen Yao
Signed-off-by: Doug Flick [MSFT]
---
.../DxeTpmMeasureBootLibSanitization.h| 23 +
.../DxeTpmMeasureBootLib.c| 13 ++-
.../DxeTpmMeasureBootLibSanitization.c
This commit contains the patch files and tests for DxeTpm2MeasureBootLib
CVE 2022-36764.
Cc: Jiewen Yao
Signed-off-by: Doug Flick [MSFT]
---
.../DxeTpm2MeasureBootLibSanitization.h | 28 -
.../DxeTpm2MeasureBootLib.c | 12 ++--
.../DxeTpm2MeasureBootLibSanitizat
This commit contains the patch files and tests for DxeTpm2MeasureBootLib
CVE 2022-36763.
Cc: Jiewen Yao
Signed-off-by: Doug Flick [MSFT]
---
SecurityPkg/Test/SecurityPkgHostTest.dsc | 1 +
.../DxeTpm2MeasureBootLib.inf | 4 +-
...Tpm2MeasureBootLibSanitizationTestHost.
This patch series include the combined / merged security patches
(as seperate commits) for TCBZ4117 (CVE-2022-36763) and TCBZ4118
(CVE-2022-36764) for DxeTpm2MeasureBootLib and DxeTpmMeasureBootLib.
These patches have already been reviewed by SecurityPkg Maintainer
(Jiewen) on GHSA.
This patch se
This creates / adds a security file that tracks the security fixes
found in this package and can be used to find the fixes that were
applied.
Cc: Jiewen Yao
Signed-off-by: Doug Flick [MSFT]
---
SecurityPkg/SecurityFixes.yaml | 22 ++
1 file changed, 22 insertions(+)
create
This commit contains the patch files and tests for DxeTpmMeasureBootLib
CVE 2022-36763.
Cc: Jiewen Yao
Signed-off-by: Doug Flick [MSFT]
---
SecurityPkg/Test/SecurityPkgHostTest.dsc | 1 +
.../DxeTpmMeasureBootLib.inf | 4 +-
...eTpmMeasureBootLibSanitizationTestHost.i
Agreed. Basically every API that takes an EF_HANDLE as input calls that API to
make sure it is a valid handle.
The first question is if we get value from making sure the EFI_HANDLE is a
member of the active set of handles.
A simple signature check in the EFI_HANDLE may be enough as long as all
> On Jan 12, 2024, at 8:37 AM, Michael D Kinney
> wrote:
>
> Hi Pedro,
>
> Thank you for evaluating this idea change from linked list to improve
> performance of the handle database.
>
> The concept of using integers for an EFI_HANDLE has been considered before.
> One advantage over pointers
> On Jan 12, 2024, at 6:46 AM, Pedro Falcato wrote:
>
> On Fri, Jan 12, 2024 at 9:35 AM Laszlo Ersek wrote:
>>
>> On 1/12/24 03:10, Pedro Falcato wrote:
>>> My idea was to make each handle an index - like a file descriptor -
>>> AFAIK there's no reason why it *needs* to be an actual pointer.
Thanks Gerd,
I'll pull that change into a separate commit and resubmit.
Best,
Thomas
On Fri, Jan 12, 2024 at 3:47 AM Gerd Hoffmann wrote:
> Hi,
>
> > diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc
> b/OvmfPkg/CloudHv/CloudHvX64.dsc
> > index af594959a9..b522fa1059 100644
> > --- a/OvmfPkg/Cloud
Hi Pedro,
Thank you for evaluating this idea change from linked list to improve
performance of the handle database.
The concept of using integers for an EFI_HANDLE has been considered before.
One advantage over pointers is that a guarantee can be made that an EFI_HANDLE
value can be guaranteed to
Enable ACPI CPPC mechanism for RD-Fremont as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with LCP to set
the desired performance. RD-Frem
RD-Fremont platform supports two LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). The cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.
Signed-off-by: Prabin CA
---
Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a
16 core platform with Poseidon CPU. Each of the CPUs include
64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache.
The platform also includes system level cache of 32MB and 8GB of RAM.
Signed-off-by: Prabin CA
---
Platf
The RD-Fremont fixed virtual platform simulates 16 CPUs and 8GB of RAM.
Add initial support for this platform by adding the required platform
build configuration files. This platform has considerable differences in
its memory map compared to its predecessors. So add a corresponding
memory map file
From: Shriram K
RD-Fremont is the next platform in the Arm's reference design platform
series. This platform includes 32 CPUs but the fixed virtual platform
(FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in
the system and so the FVP simulates 16 clusters. In preparation for
Introducing a flag called PCIE_ENABLE, which can be set to TRUE or
FALSE from the respective .dsc files to enable or disable the
PCIe support. As not all reference design platforms have PCIe support
enabled, this flag is introduced.
Signed-off-by: Prabin CA
---
Platform/ARM/SgiPkg/SgiPlatform.de
In preparation of adding the next generation of reference design
platform that have different memory map, refactor the
PcdSystemMemoryBase and PcdSystemMemorySize PCD definitions from the
common PCD definitions file into the various platform generation
specific memory map PCD definitions file.
Sig
From: Vivek Gautam
On RD-N2 and previous generation platforms, the base address was within
32-bit region. However, on upcoming platforms, the SMMUv3 base address
is beyond 32-bit address region. So, update the datatype of SMMUv3 base
PCD.
Signed-off-by: Vivek Gautam
Signed-off-by: Prabin CA
--
Changes since V1:
- Corrected memory map in the DSDT file.
This patch series introduce support for RD-Fremont reference design
platform. This platform includes 32 CPUs, but the fixed virtual platform
(FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in
the system and so the FVP
On Fri, Jan 12, 2024 at 9:35 AM Laszlo Ersek wrote:
>
> On 1/12/24 03:10, Pedro Falcato wrote:
> > My idea was to make each handle an index - like a file descriptor -
> > AFAIK there's no reason why it *needs* to be an actual pointer.
> > We'd allocate indices when creating a handle, and return th
Hi Liming,
If there are no further comments on this patch, can you let me know if I can
merge this, please?
Regards,
Sami Mujawar
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#113740): https://edk2.groups.io/g/devel/message/113740
Mu
+marcin.s.woj...@gmail.com
Hi Narinder,
czw., 21 gru 2023 o 01:54 Narinder Dhillon napisał(a):
>
> From: Narinder Dhillon
>
> New Marvell Odyssey SoC
>
> This patchset contains only the very basic elements needed to boot to
> EDK2 UiApp on Marvell Odyssey SoC
> - ARM BL31 firmware component cop
From: Pranav Madhu
The Neoverse RD-V2 FVP platform includes 16 CPUs and each CPU has 64KB
of L1 instruction/data cache, 2MB of L2 cache and 32MB of system level
cache. Extend the SMBIOS support for RD-V2 platform with this
configuration and reuse rest of the RD-N2 SMBIOS configuration for the
RD-
From: Pranav Madhu
Add RD-V2 platform identification values including the part number
and configuration number. This information will be used in populating
the SMBIOS tables.
Signed-off-by: Pranav Madhu
Signed-off-by: Prabin CA
---
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 7 +++
The Neoverse RD-N2-Cfg3 platform is a variant of RD-N2 platform with a
different mesh size and GIC ITS count. As part of the initial platform
support, add the corresponding platform and flash description files.
Use PcdPlatformVariant for the RD-N2-Cfg3 platform to specify the
platform variant. RD-N
A new PCD named PcdPlatformVariant is introduced to specify the variant
number of a platform. This PCD can be used to select platform variant
specific configurations. The default value of this PCD is 0 which
selects the base variant.
Signed-off-by: Prabin CA
---
Platform/ARM/SgiPkg/SgiPlatform.d
From: Vijayenthiran Subramaniam
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3479
A recent change in MdeModulePkg [1] introduced VariableFlashInfoLib as a
dependency to support dynamic variable flash information. Add an
instance for the library class VariableFlashInfoLib in
SgiPlatformMm.
From: Omkar Anand Kulkarni
The software executing at a higher privileged level on the reference
design platforms have been updated to allow software executing at EL1
and EL0 to access the Advanced SIMD and floating-point registers (FPEN
field of CPACR_EL1 system register is programmed to allow ac
Changes since V2:
- Removed the patch which introduce fno-stack-protector in the build flag
Changes since V1:
- Addressed comments from Sami
This patch series introduces support for two reference design platforms-
RD-N2-Cfg3 and RD-V2. The RD-N2-Cfg3 FVP platform is a variant of RD-N2
platform wi
On Fri, Jan 12, 2024 at 01:16:47PM +0100, Ard Biesheuvel wrote:
> On Fri, 12 Jan 2024 at 12:38, Gerd Hoffmann wrote:
> >
> > It is possible to find variable entries with State being 0xff,
> > i.e. not updated since flash block erase. This indicates the
> > header write was not completed (and the
+marcin.s.woj...@gmail.com
Hi Narinder,
czw., 21 gru 2023 o 01:54 Narinder Dhillon napisał(a):
>
> From: Narinder Dhillon
>
> This patch adds an EDK2 shell command to dump board configuration
> device tree.
>
> Signed-off-by: Narinder Dhillon
> ---
> .../Drivers/Fdt/FdtPlatformDxe/FdtPlatfor
On Fri, 12 Jan 2024 at 12:38, Gerd Hoffmann wrote:
>
> It is possible to find variable entries with State being 0xff,
> i.e. not updated since flash block erase. This indicates the
> header write was not completed (and therefore State was not set
> to VAR_HEADER_VALID_ONLY). Treat this as addit
On Fri, 12 Jan 2024 at 12:38, Gerd Hoffmann wrote:
>
> Raise the limit for writes without block erase from two to four
> P30_MAX_BUFFER_SIZE_IN_BYTES blocks. With this in place almost
> all efi variable updates are handled without block erase. With
> the old limit some variable updates (with dev
On Fri, 12 Jan 2024 at 12:38, Gerd Hoffmann wrote:
>
> Introduce Start and End variables to make it easier to follow the
> logic and code flow. Also replace the two NorFlashWriteBuffer calls
> with a loop containing one call.
>
> With the changes in place the code is able to handle updates larger
On Fri, 12 Jan 2024 at 12:38, Gerd Hoffmann wrote:
>
> In some cases (specifically when the flash update region is
> small but crosses a multiple of P30_MAX_BUFFER_SIZE_IN_BYTES)
> NorFlashWriteSingleBlock reads only one instead of two
> P30_MAX_BUFFER_SIZE_IN_BYTES blocks into the shadow buffer.
pt., 12 sty 2024 o 13:00 Marcin Wojtas napisał(a):
>
> +marcin.s.woj...@gmail.com
>
> Hi Narinder,
>
> czw., 21 gru 2023 o 01:54 Narinder Dhillon napisał(a):
> >
> > From: Narinder Dhillon
> >
> > This patch adds a device tree driver that is used to read board
> > configuration information fro
+marcin.s.woj...@gmail.com
Hi Narinder,
czw., 21 gru 2023 o 01:54 Narinder Dhillon napisał(a):
>
> From: Narinder Dhillon
>
> This patch adds a device tree driver that is used to read board
> configuration information from a device tree.
>
> Signed-off-by: Narinder Dhillon
> ---
> .../Drivers
Hi,
> + //
> + // 4-level paging supports translating 48-bit linear addresses to 52-bit
> physical addresses.
> + // Since linear addresses are sign-extended, the linear-address space of
> 4-level paging is:
> + // [0, 2^47-1] and [0x8000_, 0x_].
> + // So only
Hi,
> diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc
> index af594959a9..b522fa1059 100644
> --- a/OvmfPkg/CloudHv/CloudHvX64.dsc
> +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc
> @@ -566,6 +566,8 @@
># Point to the MdeModulePkg/Application/UiApp/UiApp.inf
>gEfiMdeMo
+marcin.s.woj...@gmail.com
Hi Narinder,
czw., 21 gru 2023 o 01:54 Narinder Dhillon napisał(a):
>
> From: Narinder Dhillon
>
> Marvell Odyssey SoC does not have RTC on chip. This patch provides a
> dummy RTC driver to generate architectural protocol and help boot
> Odyssey SoC.
>
> Signed-off-by
Reviewed-by: Gua Guo
From: Lean Sheng Tan
Sent: Friday, January 12, 2024 7:33:00 PM
To: Rudolph, Patrick
Cc: devel@edk2.groups.io ; Rhodes, Sean
; Guo, Gua ; Lu, James
; Ni, Ray ; Dong, Guo
Subject: Re: [PATCH] UefiPayloadPkg: CbParseLib: Fix integer overflow
It is possible to find variable entries with State being 0xff,
i.e. not updated since flash block erase. This indicates the
header write was not completed (and therefore State was not set
to VAR_HEADER_VALID_ONLY). Treat this as additional "end of
variable list" condition.
Signed-off-by: Gerd H
Raise the limit for writes without block erase from two to four
P30_MAX_BUFFER_SIZE_IN_BYTES blocks. With this in place almost
all efi variable updates are handled without block erase. With
the old limit some variable updates (with device paths) took the
block erase code path.
Signed-off-by: Ger
In some cases (specifically when the flash update region is
small but crosses a multiple of P30_MAX_BUFFER_SIZE_IN_BYTES)
NorFlashWriteSingleBlock reads only one instead of two
P30_MAX_BUFFER_SIZE_IN_BYTES blocks into the shadow buffer.
That leads to random crap being written to the second block,
Introduce Start and End variables to make it easier to follow the
logic and code flow. Also replace the two NorFlashWriteBuffer calls
with a loop containing one call.
With the changes in place the code is able to handle updates larger
than two P30_MAX_BUFFER_SIZE_IN_BYTES blocks, even though the
This is a little series containing the flash corruption fix sent
yesterday with an slightly improved commit message and some small
improvements on top of this.
Gerd Hoffmann (4):
OvmfPkg/VirtNorFlashDxe: fix shadowbuffer reads
OvmfPkg/VirtNorFlashDxe: clarify block write logic
OvmfPkg/VirtNo
+marcin.s.woj...@gmail.com
Hi Narinder
czw., 21 gru 2023 o 01:54 Narinder Dhillon napisał(a):
>
> From: Narinder Dhillon
>
> This patch adds watchdog driver for Odyssey SoC.
To make sure - isn't this watchdog IP compatible with the ARM generic
watchdog (ArmPkg/Drivers/GenericWatchdogDxe/). FYI
Hi Gua or Sean,
Would you mind to help review this?
Thanks!
Best Regards,
*Lean Sheng Tan*
9elements GmbH, Kortumstraße 19-21, 44787 Bochum, Germany
Email: sheng@9elements.com
Phone: *+49 234 68 94 188 <+492346894188>*
Mobile: *+49 176 76 113842 <+4917676113842>*
Registered office: Bochum
+marcin.s.woj...@gmail.com
Hi Narinder,
czw., 21 gru 2023 o 01:54 napisał(a):
>
> From: Narinder Dhillon
>
> This patch adds ArmPlatformLib for Marvell Odyssey SoC.
>
> Signed-off-by: Narinder Dhillon
> ---
> .../AArch64/ArmPlatformHelper.S | 86
> .../Library/ArmP
On Fri, Jan 12, 2024 at 10:47:43AM +0100, Laszlo Ersek wrote:
> On 1/11/24 14:36, Gerd Hoffmann wrote:
> > In some cases (specifically when the flash update region is
> > small but crosses a multiple of P30_MAX_BUFFER_SIZE_IN_BYTES)
> > NorFlashWriteSingleBlock reads only one instead of two
> > P30
+marcin.s.woj...@gmail.com
Hi Narinder,
czw., 21 gru 2023 o 01:54 napisał(a):
>
> From: Narinder Dhillon
>
> This patch creates ArmPlatformPkg for Odyssey SoC by overriding some of
> the files in original ArmPlatformPkg. Differences from standard
> ArmPlatformPkg are marked with "--- MRVL Overr
+marcin.s.woj...@gmail.com
Hi Narinder,
czw., 21 gru 2023 o 01:54 Narinder Dhillon napisał(a):
>
> From: Narinder Dhillon
>
> This patch provides SMC call needed by Odyssey to determine available
> memory size.
>
> Signed-off-by: Narinder Dhillon
> ---
> Silicon/Marvell/Library/SmcLib/SmcLib.
When the value type is defined as number in Redfish schema, floating
point number is allowed. RedfishCrtLib raises assert without handling
this case now. Follow the way in EDK2 to call AsciiStrDecimalToUintnS
and handle the floating point number.
Signed-off-by: Nickle Wang
Cc: Abner Chang
Cc: Ig
Hi Ray,
On Fri, Jan 12, 2024 at 09:12:34AM +, Ni, Ray wrote:
> Sunil,
> I would like to hear your feedback regarding locations of following RiscV64
> components in UefiCpuPkg:
> * UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/
> * UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/
> * UefiCpuP
Hi Ray,
OK, here I come.
[Ray] INF is a good question.
[Ray] There are two options:
[Ray] Re-use current INF file.
[Ray] Create a new INF under LoongArch64 folder.
[Ray] If the INF content can be shared a lot between different archs.
Single INF is better.
[Ray] I am just afraid some
On 1/11/24 14:36, Gerd Hoffmann wrote:
> In some cases (specifically when the flash update region is
> small but crosses a multiple of P30_MAX_BUFFER_SIZE_IN_BYTES)
> NorFlashWriteSingleBlock reads only one instead of two
> P30_MAX_BUFFER_SIZE_IN_BYTES blocks into the shadow buffer.
>
> That leads
On 1/12/24 03:44, Andrew (EFI) Fish wrote:
> Sorry need some more time to digest this…. First thoughts.
>
> 1) The actual performance issue we hit was the explosion
> of CoreValidateHandle() calls as the number of protocols got large for
> some diags. The newer handles tended to be at the end of t
On 1/12/24 03:10, Pedro Falcato wrote:
> On Thu, Jan 11, 2024 at 8:46 AM Laszlo Ersek wrote:
>>
>> On 1/10/24 22:50, Pedro Falcato wrote:
>>> FWIW, can we do better than an RB tree? They're notoriously cache
>>> unfriendly...
>>
>> Sure, if someone contributes a different data structure that is s
Chao,
I just sent a mail “[edk2-devel] RFC: Folder layout change in UefiCpuPkg”
asking Sunil (RiscV64) the same thing.
INF is a good question.
There are two options:
1. Re-use current INF file.
2. Create a new INF under LoongArch64 folder.
If the INF content can be shared a lot between di
Hi Ray,
Thanks,
Chao
On 2024/1/12 16:51, Ni, Ray wrote:
Chao,
Do you mind putting the lib content under
UefiCpuPkg/Library/CpuTimerLib/LoongArch64/?
It also follows the guidelines and avoid creating too many folders under
Library folder.
No, I don't mind, do you means put the drivers or li
Sunil,
I would like to hear your feedback regarding locations of following RiscV64
components in UefiCpuPkg:
* UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/
* UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/
* UefiCpuPkg/CpuDxeRiscV64/
* UefiCpuPkg/CpuTimerDxeRiscV64/
I would like to move them
It's strange to me that ARM's MM env still allows modifying HOBs.
Thanks,
Ray
> -Original Message-
> From: Guo, Gua
> Sent: Friday, January 12, 2024 10:25 AM
> To: devel@edk2.groups.io
> Cc: Guo, Gua ; Marc Beatove ;
> Ard Biesheuvel ; Sami Mujawar
> ; Ni, Ray ; Mathews, John
> ; Gerd Hof
Reviewed-by: Ray Ni
Thanks,
Ray
> -Original Message-
> From: Tan, Dun
> Sent: Thursday, January 11, 2024 5:01 PM
> To: devel@edk2.groups.io
> Cc: Ni, Ray ; Laszlo Ersek ; Kumar,
> Rahul R ; Gerd Hoffmann
> Subject: [PATCH] UefiCpuPkg: change name of gMpInformationHobGuid2
>
> Change na
Chao,
Do you mind putting the lib content under
UefiCpuPkg/Library/CpuTimerLib/LoongArch64/?
It also follows the guidelines and avoid creating too many folders under
Library folder.
Thanks,
Ray
> -Original Message-
> From: Chao Li
> Sent: Friday, January 12, 2024 4:24 PM
> To: devel@ed
Chao,
Do you mind putting the lib content under
UefiCpuPkg/Library/MpInitLib/LoongArch64/?
It also follows the guidelines and avoid creating too many folders under
Library folder.
Thanks,
Ray
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Chao Li
> Sent: Friday, January
Hi Gerd,
I've refined the comments and the commit message. Could you please help to
review again?
Thanks,
Dun
-Original Message-
From: devel@edk2.groups.io On Behalf Of duntan
Sent: Friday, January 12, 2024 4:32 PM
To: devel@edk2.groups.io
Cc: Ni, Ray ; Laszlo Ersek ; Kumar, Rahul
R ;
Chao,
Do you mind putting the lib content under UefiCpuPkg/CpuDxe/LoongArch64/?
It also follows the guidelines and avoid creating too many folders under root
folder.
Thanks,
Ray
> -Original Message-
> From: Chao Li
> Sent: Friday, January 12, 2024 4:25 PM
> To: devel@edk2.groups.io
> Cc
Chao,
Do you mind putting the lib content under
UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch64/?
It also follows the guidelines and avoid creating too much folders under
Library folder.
Thanks,
Ray
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Chao Li
> Sent: Fr
When creating smm page table, limit maximum
supported physical addresses bits returned by
CalculateMaximumSupportAddress() to 47 if
5-Level Paging is disabled.
This commit is to avoid issue that more than
47-bit physical addresses are requested in smm
page table when 5-level paging is disabled.
4-
Add self introduction file for LoongArch virtual machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Reviewed-by: Bibo Mao
---
OvmfPkg/LoongArchVirt/Rea
Add infrastructure files to build edk2 for LoongArch QEMU virtual
machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Xianglai Li
Co-auth
Platfrom PEI module for LoongArch platfrom initialization.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Xianglai Li
Co-authored-by: Bibo Ma
Add SEC code for LoongArch virtual machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Xianglai Li
Co-authored-by: Bibo Mao
Reviewed-by:
This library provides interface related to restart and shudown the
LoongArch64 virtual machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by:
This library for PEI phase, and obtains the QemuFwCfg base address by
directly parsing the FDT, reads and writes the data in QemuFwCfg by
operating on the QemuFwCfg base address.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Ger
Add NorFlashQemuLib for LoongArch, it is referenced from ArmVirtPkg.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Xianglai Li
Co-authored-b
This library is provides real time clock for LoongArch virtual machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Baoqi Zhang
Co-authore
Add a early serial port output library into LoongArchVirt that named
EarlyFdtSerialPortLib16550, this library is referenced from
MdeModulePkg.
This library is used in the PEI phase. Since the serial port address can
not be saved in memory of the LoongArch QEMU virtual machine in the PEI
phase, the
Add a serial port hook library in LoongArchVirt named
Fdt16550SerialProtHookLib, this library is referenced from ArmVirtPkg.
LoongArch QEMU virtual machine uses register of LOONGARCH_CSR_KS1 to
transfer serial port base addres from the PEI phase to the DXE phase.
BZ: https://bugzilla.tianocore.or
This Library is used to collect APs resources, but is currently NULL
for OvmfPkg, because it is not used by the LoongArch virtual machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qi
Add a CPU timer driver named StableTimerDxe, which proviedes
EFI_TIMER_ARCH_PROTOCOL for LoongArch.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored
Moved the PlatformBootManagerLib to OvmfPkg and renamed to
PlatformBootManagerLibLight for easy use by other ARCH.
Build-tested only (with "ArmVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Cc: J
Move the PcdTerminalTypeGuidBuffer and PcdUninstallMemAttrProtocol into
OvmfPkg so other ARCH can easily use it.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Cc: Jiewen Yao
Signed-off-by: Chao Li
---
ArmVirt
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