On Thu, Oct 12, 2023 at 07:29:59PM +0100, Pedro Falcato wrote:
> On Thu, Oct 12, 2023 at 1:12 PM Sunil V L wrote:
> >
> > Hi Ray,
> >
> > On Wed, Oct 04, 2023 at 11:34:26AM -0700, Tuan Phan wrote:
> > > Introduce a PCD to control the maximum SATP mode that MMU allowed
> > > to use. This PCD helps
On Thu, Oct 12, 2023 at 1:12 PM Sunil V L wrote:
>
> Hi Ray,
>
> On Wed, Oct 04, 2023 at 11:34:26AM -0700, Tuan Phan wrote:
> > Introduce a PCD to control the maximum SATP mode that MMU allowed
> > to use. This PCD helps RISC-V platform set bare or minimum SATP mode
> > during bring up to debug
Hi Ray,
On Wed, Oct 04, 2023 at 11:34:26AM -0700, Tuan Phan wrote:
> Introduce a PCD to control the maximum SATP mode that MMU allowed
> to use. This PCD helps RISC-V platform set bare or minimum SATP mode
> during bring up to debug memory map issue.
>
Could you help with review of this?
On Wed, Oct 04, 2023 at 11:34:26AM -0700, Tuan Phan wrote:
> Introduce a PCD to control the maximum SATP mode that MMU allowed
> to use. This PCD helps RISC-V platform set bare or minimum SATP mode
> during bring up to debug memory map issue.
>
> Signed-off-by: Tuan Phan
> Reviewed-by: Dhaval
Introduce a PCD to control the maximum SATP mode that MMU allowed
to use. This PCD helps RISC-V platform set bare or minimum SATP mode
during bring up to debug memory map issue.
Signed-off-by: Tuan Phan
Reviewed-by: Dhaval Sharma
---
Changes:
V2
- Changed default mode to SV57
