On Mon, Dec 4, 2023 at 8:30 AM Dhaval Sharma wrote:
>
> Use newly defined cache management operations for RISC-V where possible
> It builds up on the support added for RISC-V cache management
> instructions in BaseLib.
> Cc: Michael D Kinney
> Cc: Liming Gao
> Cc: Zhiguang Liu
> Cc: Laszlo
On Mon, Dec 11, 2023 at 3:20 PM Sunil V L wrote:
>
> On Mon, Dec 11, 2023 at 03:09:19PM +, Pedro Falcato wrote:
> > On Mon, Dec 11, 2023 at 1:12 PM Sunil V L wrote:
> > >
> > > On Sun, Dec 10, 2023 at 07:51:12PM +0530, Dhaval Sharma wrote:
> > [...]
> > > > nit: Can we pick a log style here?
On Mon, Dec 11, 2023 at 03:09:19PM +, Pedro Falcato wrote:
> On Mon, Dec 11, 2023 at 1:12 PM Sunil V L wrote:
> >
> > On Sun, Dec 10, 2023 at 07:51:12PM +0530, Dhaval Sharma wrote:
> [...]
> > > nit: Can we pick a log style here? Like :
> > > In this case, "CacheOpCacheRange: Performing
On Mon, Dec 11, 2023 at 1:12 PM Sunil V L wrote:
>
> On Sun, Dec 10, 2023 at 07:51:12PM +0530, Dhaval Sharma wrote:
[...]
> > nit: Can we pick a log style here? Like :
> > In this case, "CacheOpCacheRange: Performing ...". It's just prettier
> > and more greppable.
> > My interpretation of this
On Sun, Dec 10, 2023 at 07:51:12PM +0530, Dhaval Sharma wrote:
> Thanks for the review. My comments inline:
>
> On Fri, Dec 8, 2023 at 9:58 AM Sunil V L wrote:
>
> > On Thu, Dec 07, 2023 at 10:31:48AM +0530, Dhaval Sharma wrote:
> > > Comments inline:
> > >
> > >
> > > On Wed, Dec 6, 2023 at
Thanks for the review. My comments inline:
On Fri, Dec 8, 2023 at 9:58 AM Sunil V L wrote:
> On Thu, Dec 07, 2023 at 10:31:48AM +0530, Dhaval Sharma wrote:
> > Comments inline:
> >
> >
> > On Wed, Dec 6, 2023 at 7:50 PM Sunil V L
> wrote:
> >
> > > Hi Dhaval,
> > >
> > > Thank you very much
On Thu, Dec 07, 2023 at 10:31:48AM +0530, Dhaval Sharma wrote:
> Comments inline:
>
>
> On Wed, Dec 6, 2023 at 7:50 PM Sunil V L wrote:
>
> > Hi Dhaval,
> >
> > Thank you very much for fixing the issue with instruction cache
> > invalidation and confirming with the spec owner. Few minor
Comments inline:
On Wed, Dec 6, 2023 at 7:50 PM Sunil V L wrote:
> Hi Dhaval,
>
> Thank you very much for fixing the issue with instruction cache
> invalidation and confirming with the spec owner. Few minor comments
> below.
>
> On Mon, Dec 04, 2023 at 01:59:49PM +0530, Dhaval Sharma wrote:
>
Hi Dhaval,
Thank you very much for fixing the issue with instruction cache
invalidation and confirming with the spec owner. Few minor comments
below.
On Mon, Dec 04, 2023 at 01:59:49PM +0530, Dhaval Sharma wrote:
> Use newly defined cache management operations for RISC-V where possible
> It
Use newly defined cache management operations for RISC-V where possible
It builds up on the support added for RISC-V cache management
instructions in BaseLib.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
Acked-by: Laszlo Ersek
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