Hello Milkymisters (and milkymadams),
I'm proud to announce that the Milkymist MMU is making small progresses :)
It seems that phase 2 is in a good shape: it passes a few tests [0] in
ISim simulation as well as on real FPGA running MMU-enabled Milkymist SoC
Phase 2 was allow MMU to generate a
Original Message
Subject: Re: Statistics: May 2012
Date: Sat, 2 Jun 2012 03:22:07 +0200
From: Wolfgang Spraul wolfg...@sharism.cc
Reply-To: English Qi Hardware mailing list - support, developers, use
cases and fun discuss...@lists.en.qi-hardware.com
To: English Qi Hardware
Signed-off-by: Michael Walle mich...@walle.cc
---
Changes:
v2:
- fix indentation
- add defaults for PC_ex and next_irq_ack to avoid inferring latches
cores/softusb/navre_regress/tb_regress.v |2 +
.../navre_regress/test_opcodes/test_BCLR.py|2 +-
This is fabulous!
On Mon, Jun 4, 2012 at 1:24 AM, Yann Sionneau y...@minet.net wrote:
Hello Milkymisters (and milkymadams),
I'm proud to announce that the Milkymist MMU is making small progresses :)
It seems that phase 2 is in a good shape: it passes a few tests [0] in
ISim simulation as
Yann Sionneau wrote:
Phase 2 was allow MMU to generate a CPU exception upon a page fault.
Very good !
One thing that we'll need is a way to track a page's dirty
status. There are two ways to do this:
1) have a dirty bit (in this case in the TLB) the gateware sets,
or
2) initially make the
