> On 8 Jul 2022, at 6:15 pm, Sebastian Huber
> wrote:
>
> On 08.07.22 09:55, Chris Johns wrote:
>> I have finally managed to test this patch and it does not work on a
>> secure/non-secure Versal. I did a `distclean configure` and rebuild so it
>> would
>> pick up the option changes.
>> The `B
On 08.07.22 09:55, Chris Johns wrote:
I have finally managed to test this patch and it does not work on a
secure/non-secure Versal. I did a `distclean configure` and rebuild so it would
pick up the option changes.
The `BSP_ARM_GIC_ICC_IGRPEN0 write is still in the build and it is a secure
acces
Hi,
I have finally managed to test this patch and it does not work on a
secure/non-secure Versal. I did a `distclean configure` and rebuild so it would
pick up the option changes.
The `BSP_ARM_GIC_ICC_IGRPEN0 write is still in the build and it is a secure
access:
/* Initialize the group 0 and
On 05/07/2022 00:28, Chris Johns wrote:
On 4/7/2022 4:06 pm, Sebastian Huber wrote:
On 04/07/2022 03:43, Chris Johns wrote:
On 1/7/2022 11:21 pm, Sebastian Huber wrote:
Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
enable registers. This fixes the build for the
On 4/7/2022 4:06 pm, Sebastian Huber wrote:
> On 04/07/2022 03:43, Chris Johns wrote:
>> On 1/7/2022 11:21 pm, Sebastian Huber wrote:
>>> Use the existing WRITE_SR() abstraction to access the interrupt group 0 and
>>> 1
>>> enable registers. This fixes the build for the AArch32 target.
>>> ---
>>
On 04/07/2022 03:43, Chris Johns wrote:
On 1/7/2022 11:21 pm, Sebastian Huber wrote:
Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
enable registers. This fixes the build for the AArch32 target.
---
bsps/include/dev/irq/arm-gicv3.h | 30
On 1/7/2022 11:21 pm, Sebastian Huber wrote:
> Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
> enable registers. This fixes the build for the AArch32 target.
> ---
> bsps/include/dev/irq/arm-gicv3.h | 30 ---
> spec/build/bsps/aarch64/a
Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
enable registers. This fixes the build for the AArch32 target.
---
bsps/include/dev/irq/arm-gicv3.h | 30 ---
spec/build/bsps/aarch64/a53/grp.yml | 2 ++
spec/build/bsps/aarch64/a
