On Thu, Oct 13, 2022 at 2:18 AM wrote:
>
> > On Thu, 2022-10-13 at 06:27 +0200, Sebastian Huber wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you
> > know the content is safe
> >
> > On 12/10/2022 16:36, Joel Sherrill wrote:
> > > Hi
> > >
> > > I was looking at the
> On Thu, 2022-10-13 at 06:27 +0200, Sebastian Huber wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> On 12/10/2022 16:36, Joel Sherrill wrote:
> > Hi
> >
> > I was looking at the bsp default settings for sparc/leon3 to show
> > someone
Hi Joel,
We can do like below to remove visibility of RISCV_BOOT_HARTID from
other architecture configurations and only visible to RISC-V.
Changes in spec/build/cpukits
1. Remove "optboothartid" build-dependency from "cpuotps"
2. Add the "cpuriscvhartid" to
On 12/10/2022 16:36, Joel Sherrill wrote:
Hi
I was looking at the bsp default settings for sparc/leon3 to show
someone and noticed this which is out of place.
# boot hartid (processor number) of risc-v cpu (default 0)
RISCV_BOOT_HARTID = 0
I looked around and see it is an architecture
, 2022 10:36 AMTo: rtems-de...@rtems.orgSubject: Visibility of RISCV_BOOT_HARTID Hi I was looking at the bsp default settings for sparc/leon3 to show someone and noticed this which is out of place. # boot hartid (processor number) of risc-v cpu (default 0)RISCV_BOOT_HARTID = 0 I looked around
Hi
I was looking at the bsp default settings for sparc/leon3 to show someone
and noticed this which is out of place.
# boot hartid (processor number) of risc-v cpu (default 0)
RISCV_BOOT_HARTID = 0
I looked around and see it is an architecture specific ini setting but
placed in a directory with
