> On Mon, 2022-11-21 at 11:20 +0100, Sebastian Huber wrote:
>
> On 21/11/2022 11:17, padmarao.beg...@microchip.com wrote:
> > > To which number would you map the software and timer interrupts?
> > >
> > The Software and Timer interrupts(numbers 0 & 1) are mapped by
> > the Machine cause register
On 21/11/2022 11:17, padmarao.beg...@microchip.com wrote:
To which number would you map the software and timer interrupts?
The Software and Timer interrupts(numbers 0 & 1) are mapped by
the Machine cause register (mcause) and enabled by the CLINT but not by
the PLIC.
Yes, this is the
Hi Sebastian,
> On Mon, 2022-11-21 at 10:53 +0100, Sebastian Huber wrote:
>
> On 21/11/2022 10:50, padmarao.beg...@microchip.com wrote:
> > The interrupt number(vector) mention in the device tree node is
> > working
> > when the driver is used the RISCV_INTERRUPT_VECTOR_EXTERNAL() and
> > later
On 21/11/2022 10:50, padmarao.beg...@microchip.com wrote:
The interrupt number(vector) mention in the device tree node is working
when the driver is used the RISCV_INTERRUPT_VECTOR_EXTERNAL() and later
called the RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX() in the RTEMS but
the interrupt number is
Hi,
The interrupt number(vector) mention in the device tree node is working
when the driver is used the RISCV_INTERRUPT_VECTOR_EXTERNAL() and later
called the RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX() in the RTEMS but
the interrupt number is decreased by 2 when registering the interrupt
from the
