On Wednesday 27 November 2013 01:00 PM, Sourav Poddar wrote:
The patch series adds support for enabling pwm backlight, i2c2, spi and
matrix gpio keys on am43x-gp-evm.
Seems a typo - series is for epos evm.
Done on top of 3.13-rc1 + tero clock series(1)
[1]:
On Wednesday 27 November 2013 01:38 PM, Sathya Prakash wrote:
On Wednesday 27 November 2013 01:00 PM, Sourav Poddar wrote:
The patch series adds support for enabling pwm backlight, i2c2, spi and
matrix gpio keys on am43x-gp-evm.
Seems a typo - series is for epos evm.
Yes, true. The series if
Fugang Duan fugang.d...@freescale.com wrote:
From: Mark Rutland [mailto:mark.rutl...@arm.com]
Data: Tuesday, November 26, 2013 10:09 PM
To: Duan Fugang-B38611
Cc: ji...@kernel.org; sachin.ka...@linaro.org;
devicetree@vger.kernel.org;
shawn@linaro.org; Li Frank-B20596;
On 11/27/2013 05:44 AM, Fugang Duan wrote:
[...]
+ if (info-vref)
+ info-vref_uv = regulator_get_voltage(info-vref);
+ else if (of_property_read_u32(np, fsl,adc-vref, info-vref_uv))
+ dev_err(info-dev,
+ Miss adc-vref property or vref regulator in the
From: Lars-Peter Clausen [mailto:l...@metafoo.de]
Data: Wednesday, November 27, 2013 4:21 PM
To: Duan Fugang-B38611
Cc: ji...@kernel.org; sachin.ka...@linaro.org; devicetree@vger.kernel.org;
shawn@linaro.org; Li Frank-B20596; linux-...@vger.kernel.org
Subject: Re: [PATCH v3 2/3] iio:adc:imx:
+ MTD maintainers
On Tuesday 26 November 2013 01:30 AM, Ivan Khoronzhuk wrote:
The problem that the set timings code contains the call of Davinci
platform function davinci_aemif_setup_timing() which is not
accessible if kernel is built for another platform like Keystone.
The Keysone
On Wednesday, November 27, 2013 03:31 PM, Markus Pargmann wrote:
Hi,
On Wed, Nov 27, 2013 at 11:33:15AM +0800, Chris Ruehl wrote:
On Wednesday, November 20, 2013 04:01 AM, Linus Walleij wrote:
On Mon, Nov 11, 2013 at 7:19 PM, Markus Pargmannm...@pengutronix.de wrote:
Support gpio
Hi,
On Monday 25 November 2013 11:46 PM, Matt Porter wrote:
Add a driver for the internal Broadcom Kona USB 2.0 PHY found
on the BCM281xx family of SoCs.
Signed-off-by: Matt Porter matt.por...@linaro.org
---
drivers/phy/Kconfig | 6 ++
drivers/phy/Makefile| 1
From: Jonathan Cameron ji...@kernel.org
Data: Wednesday, November 27, 2013 4:10 PM
To: Duan Fugang-B38611; Mark Rutland
Cc: sachin.ka...@linaro.org; devicetree@vger.kernel.org; shawn@linaro.org;
Li Frank-B20596; linux-...@vger.kernel.org
Subject: RE: [PATCH v3 3/3] Documentation: add the
This patch allows the driver to be enabled with devicetree.
Signed-off-by: Alexander Shiyan shc_w...@mail.ru
Acked-by: Mark Rutland mark.rutl...@arm.com
---
Documentation/devicetree/bindings/rtc/maxim,ds1742.txt | 12
drivers/rtc/rtc-ds1742.c | 10
Hi,
On Monday 25 November 2013 11:46 PM, Matt Porter wrote:
Adds USB OTG/PHY and clock support to BCM281xx and enables
UDC support on the bcm11351-brt and bcm28155-ap boards.
Signed-off-by: Matt Porter matt.por...@linaro.org
Reviewed-by: Markus Mayer markus.ma...@linaro.org
Reviewed-by:
On Mon, Nov 25, 2013 at 7:32 AM, Grant Likely grant.lik...@linaro.org wrote:
On Sun, 24 Nov 2013 17:04:52 +1000, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
On Wed, Nov 13, 2013 at 4:14 PM, Grant Likely grant.lik...@linaro.org
wrote:
On Wed, 13 Nov 2013 09:17:01 +1000, Peter
On 11/26/2013 07:44 PM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [131126 00:10]:
OMAP3 platforms support both DT and non-DT boot at the moment, make
the clock init work according to the used setup.
We're making omap3 to be DT only as well, so it might make sense to
drop the omap3
On 11/26/2013 07:40 PM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [131126 00:10]:
Using regmap is required for isolating the actual memory access from
the clock code. Now, the driver providing the support for the clock IP
block can provide a regmap for this purpose.
Signed-off-by:
Hi,
sorry for the noise, but I stuck in a problem and not see whats the reason.
(old 2.6.22 kernel works)
I have a ov2640 patched for dt-support run on 0x30 at i2c1 with a power-enable
gpio.
Pinctrl setup:
pinctrl_i2c1: i2c1-1 {
fsl,pins =
-Original Message-
From: Mark Rutland [mailto:mark.rutl...@arm.com]
Sent: Monday, November 18, 2013 7:15 PM
To: Lu Jingchang-B35083
Cc: vinod.k...@intel.com; devicetree@vger.kernel.org; Wang Huan-B18965;
linux-ker...@vger.kernel.org; shawn@linaro.org; linux-arm-
On 11/27/2013 09:04 AM, Guenter Roeck wrote:
On 11/26/2013 08:31 PM, Sekhar Nori wrote:
On Monday 25 November 2013 07:34 PM, Ivan Khoronzhuk wrote:
To reduce code duplicate and increase code readability use WDT core
code to handle WDT interface.
Remove io_lock as the WDT core uses mutex to
On 11/27/2013 10:35 AM, Sekhar Nori wrote:
+ MTD maintainers
On Tuesday 26 November 2013 01:30 AM, Ivan Khoronzhuk wrote:
The problem that the set timings code contains the call of Davinci
platform function davinci_aemif_setup_timing() which is not
accessible if kernel is built for another
Lukasz Majewski wrote:
Hi Kukjin,
Hi,
Hi Kukjin,
The TMU device tree node definition for Exynos4x12 family of SoCs.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Reviewed-by: Tomasz Figa
Lukasz Majewski wrote:
Hi Kukjin,
Hi Kukjin,
This patch enables support for TMU at Exynos4412 based Trats2 board.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Reviewed-by: Tomasz Figa
This patchset does the following things
- Adds pmusysreg device node to exynos5.dtsi file
- Adds watchdog DT nodes to Exynos5250 and 5420
- Uses syscon regmap interface to configure pmu registers
to mask/unmask enable/disable of watchdog.
This patch set
This patch adds pmusysreg node to exynos5250 and exynos5420 dtsi files to
handle PMU register accesses in a centralized way using syscon driver
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
In Exynos5 series SoCs, PMU has registers to enable/disable mask/unmask
watchdog timer which is not the case with s3c series SoCs so, there is a
need to have different compatible names for watchdog to handle these pmu
registers access.
Hence this patch removes watchdog node from Exynos5.dtsi
On 11/27/2013 03:33 AM, Brian Norris wrote:
Hi Ivan,
On Thu, Nov 21, 2013 at 01:28:15PM +0200, Ivan Khoronzhuk wrote:
This series contains fixes and updates of Davinci nand driver in
order to reuse it for Keystone platform.
The series is combination of two following series:
- Davinci nand
On 11/26/2013 11:34 PM, Alexander Shiyan wrote:
Hello.
On 11/26/2013 08:26 AM, Alexander Shiyan wrote:
This patch adds a watchdog driver for devices controlled through GPIO,
(Analog Devices ADM706, IC 555 etc).
Signed-off-by: Alexander Shiyan shc_w...@mail.ru
...
+++
Hi kg...@kernel.org,
Lukasz Majewski wrote:
Hi Kukjin,
Hi,
Hi Kukjin,
The TMU device tree node definition for Exynos4x12 family of
SoCs.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Reviewed-by: Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com
Hello,
This patch series adds support for clock accuracy retrieval in the common clk
framework.
Best Regards,
Boris
Changes since v1:
- remove HAVE_CLK_GET_ACCURACY option and enable clk accuracy support only
when using the CCF
- export __clk_get_accuracy (might be used by clk-providers)
These patches are intended to update Davinci watchdog to use WDT core
and reuse driver for keystone arch, because Keystone uses the similar
IP like Davinci.
See Documentation:
Davinci DM646x - http://www.ti.com/lit/ug/spruer5b/spruer5b.pdf
Keystone - http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
The keystone arch uses the same IP watchdog, so add ti,keystone-wdt
compatible and correct identity.
The Keystone arch is using clocks in DT and source clock for watchdog
has to be specified, so add this to binding.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter Roeck
Some SoCs, like Keystone 2, can support more than one WDT and each
watchdog device has to use it's own base address, clock source,
watchdog device, so add new davinci_wdt_device structure to hold
device data.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter roeck
To reduce code duplicate and increase code readability use WDT core
code to handle WDT interface.
Remove io_lock as the WDT core uses mutex to lock each wdt device.
Remove wdt_state as the WDT core tracks state with its own variable.
The watchdog_init_timeout() can read timeout value from
Currently, the davinci watchdog can be read while counting,
so we can add ability to report the remaining time before
the system will reboot.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter Roeck li...@roeck-us.net
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Since Davinci WDT has been switched to use WDT core, it became able
to support timeout-sec property, so add it to it's binding description.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Guenter Roeck li...@roeck-us.net
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
The clock accuracy is expressed in ppb (parts per billion) and represents
the possible clock drift.
Say you have a clock (e.g. an oscillator) which provides a fixed clock of
20MHz with an accuracy of +- 20Hz. This accuracy expressed in ppb is
20Hz/20MHz = 1000 ppb (or 1 ppm).
Clock users may need
This patch adds support for accuracy retrieval on fixed clocks.
It also adds a new dt property called 'clock-accuracy' to define the clock
accuracy.
This can be usefull for oscillator (RC, crystal, ...) definitions which are
always given an accuracy characteristic.
Signed-off-by: Boris BREZILLON
On Wednesday 27 November 2013 04:31 PM, ivan.khoronzhuk wrote:
@@ -192,9 +193,15 @@ static __init void davinci_ntosd2_init(void)
davinci_cfg_reg(DM644X_ATAEN_DISABLE);
/* only one device will be jumpered and detected */
-if (HAS_NAND)
+if (HAS_NAND) {
MAX14577 chip is a multi-function device which includes MUIC,
charger and voltage regulator. The driver is located in drivers/mfd.
This patch adds regulator driver for MAX14577 chip. There are two
regulators in this chip:
1. Safeout LDO with constant voltage output of 4.9V. It can be only
On Fri, 22 Nov 2013, Krzysztof Kozlowski wrote:
From: Chanwoo Choi cw00.c...@samsung.com
This patch adds max14577 core/irq driver to support MUIC(Micro USB IC)
device and charger device and support irq domain method to control
internal interrupt of max14577 device. Also, this patch supports
On 11/27/2013 03:07 PM, Sekhar Nori wrote:
On Wednesday 27 November 2013 04:31 PM, ivan.khoronzhuk wrote:
@@ -192,9 +193,15 @@ static __init void davinci_ntosd2_init(void)
davinci_cfg_reg(DM644X_ATAEN_DISABLE);
/* only one device will be jumpered and detected */
-
Hello everyone,
The Samsung SoCs from Exynos family are enhanced with a bunch of switches
dedicated for IP blocks. Those switches are called PHYs in Exynos
specification. They are usually controlled by a single bit in a single
one-word-long register.
A IP driver has to control such a switch in an
Add exynos-phy driver to support a single register
PHY interfaces present on Exynos4 SoC.
Signed-off-by: Tomasz Stanislawski t.stanisl...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/phy/Kconfig |5 ++
drivers/phy/Makefile |1 +
As we switch to use the watchdog core which permits more than one
active watchdog in the system, rename platform driver to
davinci-wdt to be identifiable.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
based on:
https://lkml.org/lkml/2013/11/27/164
CC:
Sekhar Nori nsek...@ti.com
Add document describing device tree bindings for MAX14577 MFD driver.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Documentation/devicetree/bindings/mfd/max14577.txt | 48
1 file changed, 48
MAX14577 chip is a multi-function device which includes MUIC,
charger and voltage regulator. The driver is located in drivers/mfd.
This patch adds regulator driver for MAX14577 chip. There are two
regulators in this chip:
1. Safeout LDO with constant voltage output of 4.9V. It can be only
On Wednesday 27 November 2013 09:00 AM, Sekhar Nori wrote:
On Wednesday 27 November 2013 07:01 PM, Ivan Khoronzhuk wrote:
As we switch to use the watchdog core which permits more than one
active watchdog in the system, rename platform driver to
davinci-wdt to be identifiable.
Signed-off-by:
On Wed, Nov 27, 2013 at 05:37:24AM +, Fugang Duan wrote:
From: Mark Rutland mark.rutl...@arm.com
Data: Tuesday, November 26, 2013 10:26 PM
To: Duan Fugang-B38611
Cc: ji...@kernel.org; sachin.ka...@linaro.org; devicetree@vger.kernel.org;
shawn@linaro.org; Li Frank-B20596;
The problem that the set timings code contains the call of Davinci
platform function davinci_aemif_setup_timing() which is not
accessible if kernel is built for another platform like Keystone.
The Keysone platform is going to use TI AEMIF driver.
If TI AEMIF is used we don't need to set timings
Hi,
On Wed, Nov 27, 2013 at 03:49:52AM +, th...@altera.com wrote:
From: Tien Hock Loh th...@altera.com
Add driver support for Altera GPIO soft IP, including interrupts and I/O.
Tested on Altera CV SoC board using dipsw and LED using LED framework.
Signed-off-by: Tien Hock Loh
Boris,
Thanks for posting this series. Bear with me as I'm attempting to give
MikeT a hand. Don't be afraid to tell me a question is stupid :-)
On Wed, Nov 27, 2013 at 01:44:45PM +0100, Boris BREZILLON wrote:
This patch adds support for accuracy retrieval on fixed clocks.
It also adds a new
On Thu, 21 Nov 2013 17:23:14 -0600, Rob Herring robherri...@gmail.com wrote:
On Thu, Nov 21, 2013 at 6:50 AM, Grant Likely grant.lik...@linaro.org wrote:
On Wed, 30 Oct 2013 01:12:51 -0500, Rob Herring robherri...@gmail.com
wrote:
From: Rob Herring rob.herr...@calxeda.com
Add
On Wed, 27 Nov 2013, Mark Brown wrote:
On Wed, Nov 27, 2013 at 02:46:21PM +0100, Krzysztof Kozlowski wrote:
+ {
+ .name = max14577-regulator,
+ .of_compatible = maxim,max14577-regulator,
+ },
Why is there a compatible for this at all, would this ever appear
The following devices/functionalities were added:
* Main and secondary UARTs.
* i2c and the pcf8563 device.
* Ethernet.
* NAND.
* The BP1 button.
* The LED.
* Watchdog.
* SD.
* USB host.
Cc: Rob Herring rob.herr...@calxeda.com
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland
On Thu, 21 Nov 2013 18:49:08 +0100, Geert Uytterhoeven ge...@linux-m68k.org
wrote:
On Thu, Nov 21, 2013 at 4:53 PM, Grant Likely grant.lik...@secretlab.ca
wrote:
My changes don't change the current behavior much: currently
early_init_dt_scan() is already called with __dtb_start in several
Cc: Thierry Reding thierry.red...@gmail.com
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring rob.herr...@calxeda.com
Cc: devicetree@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: Samuel Ortiz sa...@linux.intel.com
Cc: Lee Jones lee.jo...@linaro.org
Cc: Shawn Guo shawn@linaro.org
Cc:
The eukrea mbimx53sd has its display backlighgt
connected to the pwm of its mc13xxx, so we turn
it on.
Cc: Thierry Reding thierry.red...@gmail.com
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring rob.herr...@calxeda.com
Cc: devicetree@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc:
Cc: Thierry Reding thierry.red...@gmail.com
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring rob.herr...@calxeda.com
Cc: devicetree@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: Samuel Ortiz sa...@linux.intel.com
Cc: Lee Jones lee.jo...@linaro.org
Cc: Shawn Guo shawn@linaro.org
Cc:
On Wed, Nov 27, 2013 at 03:23:58PM +, Lee Jones wrote:
On Wed, 27 Nov 2013, Mark Brown wrote:
+ {
+ .name = max14577-regulator,
+ .of_compatible = maxim,max14577-regulator,
+ },
Why is there a compatible for this at all, would this ever appear as
part of a
Cc: Rob Herring rob.herr...@calxeda.com
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Stephen Warren swar...@wwwdotorg.org
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc: devicetree@vger.kernel.org
Cc: Liam Girdwood lgirdw...@gmail.com
Cc: Mark Brown
On Mon, 25 Nov 2013 10:25:50 +0100, Thierry Reding thierry.red...@gmail.com
wrote:
On Sun, Nov 24, 2013 at 09:36:51PM +, Grant Likely wrote:
On Fri, 22 Nov 2013 16:43:35 -0800, Tony Lindgren t...@atomide.com wrote:
Currently we get the following kind of errors if we try to use
Cc: Rob Herring rob.herr...@calxeda.com
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Stephen Warren swar...@wwwdotorg.org
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc: devicetree@vger.kernel.org
Cc: Liam Girdwood lgirdw...@gmail.com
Cc: Mark Brown
Cc: Rob Herring rob.herr...@calxeda.com
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Stephen Warren swar...@wwwdotorg.org
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc: devicetree@vger.kernel.org
Cc: Liam Girdwood lgirdw...@gmail.com
Cc: Mark Brown
Hello.
...
Signed-off-by: Denis Carikli de...@eukrea.com
---
.../devicetree/bindings/pwm/fsl,mc13xxx-pwm.txt| 19 ++
drivers/mfd/mc13xxx-core.c | 11 ++
drivers/pwm/Kconfig|6 +
drivers/pwm/Makefile
On Mon, 25 Nov 2013 10:49:55 +0100, Thierry Reding thierry.red...@gmail.com
wrote:
On Mon, Nov 25, 2013 at 10:25:50AM +0100, Thierry Reding wrote:
On Sun, Nov 24, 2013 at 09:36:51PM +, Grant Likely wrote:
On Fri, 22 Nov 2013 16:43:35 -0800, Tony Lindgren t...@atomide.com
wrote:
On 11/27/2013 05:31 AM, Ivan Khoronzhuk wrote:
As we switch to use the watchdog core which permits more than one
active watchdog in the system, rename platform driver to
davinci-wdt to be identifiable.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Reviewed-by: Guenter Roeck
On 11/27/2013 06:00 AM, Sekhar Nori wrote:
On Wednesday 27 November 2013 07:01 PM, Ivan Khoronzhuk wrote:
As we switch to use the watchdog core which permits more than one
active watchdog in the system, rename platform driver to
davinci-wdt to be identifiable.
Signed-off-by: Ivan Khoronzhuk
Hi
+struct mc13xxx *get_mc13xxx(void)
+{
+ return mc13xxx_data;
+}
+EXPORT_SYMBOL_GPL(get_mc13xxx);
+
int mc13xxx_common_init(struct mc13xxx *mc13xxx,
struct mc13xxx_platform_data *pdata, int irq)
{
@@ -706,6 +714,9 @@ err_revision:
On Wed, 27 Nov 2013, Mark Brown wrote:
On Wed, Nov 27, 2013 at 03:23:58PM +, Lee Jones wrote:
On Wed, 27 Nov 2013, Mark Brown wrote:
+ {
+ .name = max14577-regulator,
+ .of_compatible = maxim,max14577-regulator,
+ },
Why is there
On Wed, Nov 27, 2013 at 04:13:23PM +, Lee Jones wrote:
On Wed, 27 Nov 2013, Mark Brown wrote:
The usual thing to do is of_get_child_by_name() on the parent to get the
container to search in.
What do you mean when you say 'usual thing'? Only the max8998 does
this currently. IMHO the
On Wednesday 27 November 2013 03:25 AM, Tony Lindgren wrote:
* Dan Murphy dmur...@ti.com [131121 09:28]:
On 11/21/2013 10:58 AM, Tony Lindgren wrote:
* Balaji T K balaj...@ti.com [131121 05:51]:
pin mux wl12xx_gpio and wl12xx_pins should be part of omap4_pmx_core
and not omap4_pmx_wkup. So,
On Tue, Nov 26, 2013 at 03:46:26PM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Monday 25 November 2013 11:45 PM, Matt Porter wrote:
This adds a pair of APIs that allows the generic PHY subsystem to
provide information on the PHY bus width. The PHY provider driver may
use
On Tue, Nov 26, 2013 at 03:49:30PM +0530, Kishon Vijay Abraham I wrote:
On Monday 25 November 2013 11:46 PM, Matt Porter wrote:
dwc2/s3c-hsotg require a single clock to be specified and optionally
a generic phy. On the s3c-hsotg driver old style USB phy support is
present as a fallback so
On 11/27/2013 03:50 AM, Leela Krishna Amudala wrote:
Add device tree support for exynos5250 and 5420 SoCs and use syscon regmap
interface
to configure AUTOMATIC_WDT_RESET_DISABLE and MASK_WDT_RESET_REQUEST registers
of PMU
to mask/unmask enable/disable of watchdog in probe and s2r scenarios.
On Tue, Nov 26, 2013 at 03:53:32PM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Monday 25 November 2013 11:46 PM, Matt Porter wrote:
If a generic phy is present, call phy_init()/phy_exit(). This supports
generic phys that must be soft reset before power on.
Signed-off-by: Matt Porter
On Tue, Nov 26, 2013 at 03:58:45PM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Monday 25 November 2013 11:46 PM, Matt Porter wrote:
Adds support for querying the phy bus width from the generic phy
subsystem. Configure UTMI bus width in GUSBCFG based on this value.
Signed-off-by: Matt
On Tue, Nov 26, 2013 at 04:01:05PM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Monday 25 November 2013 11:46 PM, Matt Porter wrote:
Add a binding that describes the Broadcom Kona USB2 PHY found
on the BCM281xx family of SoCs.
Signed-off-by: Matt Porter matt.por...@linaro.org
---
On Wed, Nov 27, 2013 at 02:21:52PM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Monday 25 November 2013 11:46 PM, Matt Porter wrote:
Add a driver for the internal Broadcom Kona USB 2.0 PHY found
on the BCM281xx family of SoCs.
Signed-off-by: Matt Porter matt.por...@linaro.org
---
On Wed, Nov 27, 2013 at 02:27:19PM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Monday 25 November 2013 11:46 PM, Matt Porter wrote:
Adds USB OTG/PHY and clock support to BCM281xx and enables
UDC support on the bcm11351-brt and bcm28155-ap boards.
Signed-off-by: Matt Porter
Hi all,
SoC architectures are getting increasingly complex in ways that are not
transparent to software.
A particular emerging issue is that of multi-master SoCs, which may have
different address views, IOMMUs, and coherency behaviour from one master
to the next.
DT can't describe multi-master
On Fri, Nov 15, 2013 at 09:35:33AM -0600, Brian Austin wrote:
This patch adds device tree support for the CS42L52 Codec
Applied both, thanks.
signature.asc
Description: Digital signature
* Tony Lindgren t...@atomide.com [131116 07:17]:
Here's what I was thinking with the reg-io-width-mask. Anybody
have comments on using reg-io-width vs reg-io-width-mask?
...
--- a/drivers/net/ethernet/smsc/smc91x.c
+++ b/drivers/net/ethernet/smsc/smc91x.c
@@ -,11 +2234,31 @@ static int
Quoting Andrew Bresticker (2013-09-25 14:12:47)
The Exynos AudioSS clock controller will later be modified to allow
input clocks to be specified via device-tree in order to support
multiple Exynos SoCs. This will introduce a dependency on the core
SoC clock controller being initialized first
Commit 89ce376c6bdc (drivers/net: Use of_match_ptr() macro in smc91x.c)
added minimal device tree support to smc91x, but it's not working on
many platforms because of the lack of some key configuration bits.
Fix the issue by parsing the necessary configuration like the
smc911x driver is doing. As
This adds typical McBSP2-TWL4030 audio description to the legacy
Beagle Board.
Signed-off-by: Jarkko Nikula jarkko.nik...@bitmer.com
---
arch/arm/boot/dts/omap3-beagle.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/omap3-beagle.dts
On Wed, Nov 27, 2013 at 1:49 AM, Mark Rutland mark.rutl...@arm.com wrote:
Hi Olof,
On Wed, Nov 27, 2013 at 01:52:52AM +, Olof Johansson wrote:
While the LPAE capability is determined by the kernel today, it is still
useful to be able to specify the feature in the device tree. There is
Quoting Ezequiel Garcia (2013-09-25 12:10:18)
The required properties are not named div and mult,
but rather clock-div and clock-mult.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
Taken into clk-next.
Thanks,
Mike
---
Hi Alexander,
From: Alexander Shiyan
This patch adds a property to automatically determine the NAND
bus width by CFI/ONFI information from chip. This property works
if the bus width is not specified explicitly.
Signed-off-by: Alexander Shiyan shc_w...@mail.ru
---
[...]
---
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
Acked-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/boot/dts/zynq-7000.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index e7f73b2e4550..60d155224c98
In some use cases Zynq's FPGA clocks are used as static clock
generators for IP in the FPGA part of the SOC for which no Linux driver
exists and would control those clocks. To avoid automatic
gating of these clocks in such cases a new property - fclk-enable - is
added to the clock controller's DT
Quoting Boris BREZILLON (2013-11-12 13:57:19)
+static const struct clk_ops pll_ops = {
+ .prepare = clk_pll_prepare,
+ .is_prepared = clk_pll_is_ready,
+ .disable = clk_pll_disable,
+ .is_enabled = clk_pll_is_ready,
+ .recalc_rate = clk_pll_recalc_rate,
+
* Grant Likely grant.lik...@linaro.org [131124 13:37]:
I actually like the idea of completely allocating the resource structure
but leaving some entries empty. However, I agree with rmk that putting
garbage into a resource structure is a bad idea. What about changing the
value of flags to 0
* Jarkko Nikula jarkko.nik...@bitmer.com [131127 10:48]:
This adds typical McBSP2-TWL4030 audio description to the legacy
Beagle Board.
Nice to see that work almost out of the box :)
BTW, I just noticed that sound/soc/omap/Kconfig has depends on
OMAP_MUX. The OMAP_MUX option will be dropped
Quoting Boris BREZILLON (2013-11-12 14:05:35)
This patch adds new at91 system clock implementation using common clk
framework.
Some peripherals need to enable a system clock in order to work properly.
Each system clock is given an id based on the bit position in SCER/SCDR
registers.
On Wed, Nov 27, 2013 at 12:13:25PM -0500, Matt Porter wrote:
On Tue, Nov 26, 2013 at 03:53:32PM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Monday 25 November 2013 11:46 PM, Matt Porter wrote:
If a generic phy is present, call phy_init()/phy_exit(). This supports
generic phys that
On Wed, Nov 27, 2013 at 05:28:06PM +, Dave Martin wrote:
Hi all,
SoC architectures are getting increasingly complex in ways that are not
transparent to software.
A particular emerging issue is that of multi-master SoCs, which may have
different address views, IOMMUs, and coherency
Um, do you have a definition somewhere (like in comments) of the definition
of the accuracy you're using? So multiple people can add consistent values?
Is this the standard deviation (67% confidence), 2 standard deviations
(95%), 3 (99%), or something else?
What averaging time is this computed
Hello,
This is the fourth version of the patch set adds device tree bindings for the
sh sci serial port devices and adds OF parsing to the sh-sci driver.
The bindings are based on Bastian Hecht's proposal (see
http://www.spinics.net/lists/arm-kernel/msg228129.html). The approach taken
here is
Document the device tree bindings for the sci serial port devices.
Cc: devicetree@vger.kernel.org
Signed-off-by: Laurent Pinchart laurent.pinchart+rene...@ideasonboard.com
Acked-by: Simon Horman horms+rene...@verge.net.au
---
.../bindings/serial/renesas,sci-serial.txt | 46
* Tony Lindgren t...@atomide.com [131127 08:49]:
* Balaji T K balaj...@ti.com [131127 08:30]:
On Wednesday 27 November 2013 03:25 AM, Tony Lindgren wrote:
* Dan Murphy dmur...@ti.com [131121 09:28]:
On 11/21/2013 10:58 AM, Tony Lindgren wrote:
* Balaji T K balaj...@ti.com [131121 05:51]:
On 11/26/2013 02:05 AM, Tero Kristo wrote:
Hi,
Changes compared to v9:
- rebased on top of 3.13-rc1
- modified the low level clk register API to provide SoC specific clk_readl
and clk_writel support which can be registered during boot, TI SoC variant
uses regmap on low level
- dropped
From: Mark Rutland [mailto:mark.rutl...@arm.com]
Data: Wednesday, November 27, 2013 10:18 PM
To: Duan Fugang-B38611
Cc: ji...@kernel.org; sachin.ka...@linaro.org; devicetree@vger.kernel.org;
shawn@linaro.org; Li Frank-B20596; linux-...@vger.kernel.org
Subject: Re: [PATCH v3 2/3] iio:adc:imx:
1 - 100 of 125 matches
Mail list logo
