Hello Henrik,
On 29/01/2014 23:37, Henrik Nordström wrote:
ons 2014-01-29 klockan 11:11 -0600 skrev Rob Herring:
Isn't allwinner,rb implied by a lack of rb-gpios property. Or no R/B
pin is an option? If so, don't you need some fixed time delay
properties like max erase time?
rb-gpios could
Hello Henrik,
Sorry for the noise, I sent the mail to Rob's old address.
On 29/01/2014 23:37, Henrik Nordström wrote:
ons 2014-01-29 klockan 11:11 -0600 skrev Rob Herring:
Isn't allwinner,rb implied by a lack of rb-gpios property. Or no R/B
pin is an option? If so, don't you need some fixed
On 29/01/2014 20:10, Jason Gunthorpe wrote:
On Wed, Jan 29, 2014 at 03:46:20PM -0300, Ezequiel Garcia wrote:
After CE# has been pulled high and then transitioned low again, the host
should issue a Set Features to select the appropriate asynchronous timing mode.
Oh, I had forgot you should do
Greetings,
I develop the boot-loader and kernel for a family of boards that have
an on-board EEPROM which contains information as to what options are
physically loaded on the board such as memory size/config, and
peripheral IC's. We allow customers to create special builds of our
standard
Hello,
On 30 January 2014 10:11, Tim Harvey thar...@gateworks.com wrote:
Greetings,
Is it more appropriate for the bootloader to 'remove' nodes for
devices that are not physically present or should I be setting their
status property to 'disabled' instead? I'm not clear if either option
From: Pratyush Anand pratyush.an...@st.com
ahci driver needs some platform specific functions which are called at
init, exit, suspend and resume conditions. Till now these functions were
present in a platform driver with a fixme notes.
Similar functions modifying same set of registers will also
First three patches are improvement and fixes for SPEAr13xx support.
Next patch modify phy-core driver for its initialization during
subsys_initcall(). Platform ahci driver is modified for phy hooks.
Patch#6 and 7 modify/add support for SPEAr13xx SATA and PCIe.
These patches are tested with
On 29/01/2014 15:34, Boris BREZILLON wrote:
Add support for the sunxi NAND Flash Controller (NFC).
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
drivers/mtd/nand/Kconfig |6 +
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/sunxi_nand.c | 744
On Wed, Jan 29, 2014 at 08:10:34PM +0100, Geert Uytterhoeven wrote:
On Wed, Jan 29, 2014 at 7:00 PM, Mark Brown broo...@kernel.org wrote:
well?
As there were no code changes in v5 of spi: rspi: Add DT support,
Patch [14/14] spi: rspi: Add support for Quad and Dual SPI Transfers on QSPI
At late init all unused clocks are disabled. So clocks that were not
get before will be gated. In Keysone 2 SoC we have at least one
necessary clock that is not used by any driver - msmcsram. This
clock is necessary, because it supplies the Multicore Shared Memory
Controller (MSMC). The MSMC
This patch adds the DT documentation of the NXP TDA998x CODEC.
Signed-off-by: Jean-Francois Moine moin...@free.fr
---
Documentation/devicetree/bindings/sound/tda998x.txt | 16
1 file changed, 16 insertions(+)
create mode 100644
On Thu, Aug 22, 2013 at 08:16:28PM +0530, Balaji T K wrote:
On Thursday 22 August 2013 06:26 PM, Dan Carpenter wrote:
'!' has higher precedence than '' so this doesn't work as intended
although since RESETDONE is 1 it would work if none of the other bits
are set.
Hi Dan,
Thanks for the
From: Heiko Stuebner heiko.stueb...@bqreaders.com
On i.MX, which carries a lot of pin-groups of which most are unused on
individual boards, they noticed that this plehora of nodes also results
in the runtime-lookup-performance also degrading [0].
A i.MX-specific solution defining the pingroups
Hi,
Heiko Stübner wrote:
From: Heiko Stuebner heiko.stueb...@bqreaders.com
On i.MX, which carries a lot of pin-groups of which most are unused on
individual boards, they noticed that this plehora of nodes also results
in the runtime-lookup-performance also degrading [0].
A i.MX-specific
On Thu, Jan 30, 2014 at 11:22:48AM +0530, Satish Patel wrote:
On 1/20/2014 10:03 AM, Satish Patel wrote:
Changes from v1:
* RFC(v1) comments are fixed
** removed gpio_to_irq as GPIO controller process cell from DT and
give it to DT node
** comments on documentation
** few other
Add support for the sunxi NAND Flash Controller (NFC).
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
Hello,
This version fixes a bug in the R/B GPIO config block.
The timing config order is now respected, but I'll wait for Jason work
regarding timing config in NAND core code
Add HW ECC support for the sunxi NAND Flash Controller.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
drivers/mtd/nand/sunxi_nand.c | 279 +++--
1 file changed, 266 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/nand/sunxi_nand.c
Add documentation for the ONFI NAND timing mode property.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
---
Changes since v2:
- fix description of the nand-timing-mode property: the mode property is
a mask containing all supported modes, each mode is encoded as a bit
position
On Mon, Jan 13, 2014 at 5:56 PM, Alexander Shiyan shc_w...@mail.ru wrote:
SYSCON driver was designed for using memory areas (registers)
that are used in several subsystems. There are systems (CPUs)
which use bits in one register for various purposes and thus
should be handled by various
Ok. I will delete node for this clock from DT and send v1
On 01/30/2014 03:25 PM, Shilimkar, Santosh wrote:
Disable is not good idea since it conveys wrong info
Hyperlink case was different.
Sent from my Android phone using TouchDown (www.nitrodesk.com)
-Original Message-
*From:*
On Friday 24 January 2014, Tanmay Inamdar wrote:
+ pcie3: pcie@1f50 {
+ reg-names = csr, cfg;
+ ranges = 0x0100 0x0 0x 0xa0 0x
0x0 0x0001 /* mem */
+ 0x0200 0x0
On Friday 24 January 2014, Tanmay Inamdar wrote:
+static void xgene_pcie_fixup_bridge(struct pci_dev *dev)
+{
+ int i;
+
+ /* Hide the PCI host BARs from the kernel as their content doesn't
+ * fit well in the resource management
+ */
+ for (i = 0; i
On Friday 24 January 2014, Tanmay Inamdar wrote:
This patch adds support for AppliedMicro X-Gene PCIe host controller. The
driver is tested on X-Gene platform with different gen1/2/3 PCIe endpoint
cards.
X-Gene PCIe controller driver has depedency on the pcie arch support for
arm64. The
From: Heiko Stuebner heiko.stueb...@bqreaders.com
Neonode Inc. is the Manufacturer of the zforce infraread touchscreens
used in a lot of ebook readers and supported by the zforce_ts driver.
Signed-off-by: Heiko Stuebner heiko.stueb...@bqreaders.com
---
Dmitry, the input maintainer, didn't want
On Thursday 30 January 2014, Tanmay Inamdar wrote:
When you repost, please make sure you fix whatever problem is
preventing your email from appearing on the vger mailing lists. I
won't apply things that haven't appeared on the linux-pci list,
because that list is the opportunity for
On Thursday 30 January 2014 08:58 AM, Ivan Khoronzhuk wrote:
Ok. I will delete node for this clock from DT and send v1
Sorry for the html reply first of all. That node should never have
been actually added since the clock is not suppose to be touched even
in low power states. Change log should
Add routines for 8, 16 and 32-bit access like in sja1000_platform.c
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc: Kumar Gala
Add the reg-io-width property to describe the width of the memory
accesses.
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc: Kumar Gala
On Tuesday 28 January 2014, Ravi Patel wrote:
On Tue, Jan 14, 2014 at 7:15 AM, Arnd Bergmann a...@arndb.de wrote:
-
For the DT binding, I would suggest using something along the lines of
what we have for clocks, pinctrl and dmaengine. OMAP doesn't use this
(yet), but now would be a good
On Thu, Jan 30, 2014 at 8:29 AM, Florian Vaussard
florian.vauss...@epfl.ch wrote:
Add the reg-io-width property to describe the width of the memory
accesses.
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland
Boris,
Can you please explain to me why you mail all your patches _To:_ me?
As in, why do I appear in the To: line of all the patches you seem to
mail out, whether or not they're relevant to me. I see this very
regularly from you - virtually all patches I see on the LAKML mailing
list from you
From: Alexandre TORGUE alexandre.tor...@st.com
This patch adds support to STiD127 SoC.
The main adaptation is the L2 cache way size compare to STiH41x SoCs.
Signed-off-by: alexandre torgue alexandre.tor...@st.com
Signed-off-by: Patrice Chotard patrice.chot...@st.com
---
From: Alexandre TORGUE alexandre.tor...@st.com
Add support for B2112 board based on STiD127 SoC.
Signed-off-by: Alexandre Torgue alexandre.tor...@st.com
Signed-off-by: Maxime Coquelin maxime.coque...@st.com
---
arch/arm/boot/dts/Makefile |3 ++-
arch/arm/boot/dts/stid127-b2112.dts
Hello Russel,
On 30/01/2014 15:36, Russell King - ARM Linux wrote:
Boris,
Can you please explain to me why you mail all your patches _To:_ me?
As in, why do I appear in the To: line of all the patches you seem to
mail out, whether or not they're relevant to me. I see this very
regularly from
From: Alexandre TORGUE alexandre.tor...@st.com
Add STid127 PIOs (psouth, pwest, peast) in pinctrl.
Signed-off-by: alexandre torgue alexandre.tor...@st.com
---
drivers/pinctrl/pinctrl-st.c | 25 +
1 file changed, 25 insertions(+)
diff --git
mach-virt has existed for a while but it is not written down what it actually
consists of. Although it seems a bit unusual to document a binding for an
entire platform since mach-virt is entirely virtual it is helpful to have
something to refer to in the absence of a single concrete
Hi Ian,
On 01/30/2014 11:11 AM, Ian Campbell wrote:
mach-virt has existed for a while but it is not written down what it actually
consists of. Although it seems a bit unusual to document a binding for an
entire platform since mach-virt is entirely virtual it is helpful to have
something to
Hi,
Apologies for the delayed reply.
On 12/09/2013 11:38 AM, Mark Rutland wrote:
On Fri, Dec 06, 2013 at 11:59:46AM +, Georgi Djakov wrote:
On 12/05/2013 11:52 AM, Mark Rutland wrote:
[...]
+
+- qcom,{vdd,vdd-io}-lpm-sup - specifies whether the supply can be kept in low
power mode.
On 12/09/2013 11:46 AM, Mark Rutland wrote:
[...]
+ /*
+* CORE_SW_RST above may trigger power irq if previous status of PWRCTL
+* was either BUS_ON or IO_HIGH_V. So before we enable the power irq
+* interrupt in GIC (by registering the interrupt handler), we need
Thanks, I will send v2
On 01/30/2014 04:31 PM, Santosh Shilimkar wrote:
On Thursday 30 January 2014 08:58 AM, Ivan Khoronzhuk wrote:
Ok. I will delete node for this clock from DT and send v1
Sorry for the html reply first of all. That node should never have
been actually added since the
On Thu, 30 Jan 2014, Christopher Covington wrote:
Hi Ian,
On 01/30/2014 11:11 AM, Ian Campbell wrote:
mach-virt has existed for a while but it is not written down what it
actually
consists of. Although it seems a bit unusual to document a binding for an
entire platform since mach-virt
Hi Ian,
On 30/01/14 16:11, Ian Campbell wrote:
mach-virt has existed for a while but it is not written down what it actually
consists of. Although it seems a bit unusual to document a binding for an
entire platform since mach-virt is entirely virtual it is helpful to have
something to refer
On Thu, 2014-01-30 at 11:54 -0500, Christopher Covington wrote:
+++ b/Documentation/devicetree/bindings/arm/mach-virt.txt
@@ -0,0 +1,32 @@
+* Mach-virt Dummy Virtual Machine platform
+
+mach-virt is the smallest, dumbest platform possible, to be used as
+a guest for Xen, KVM and other
Hi,
Apologies for the delayed reply.
On 12/09/2013 07:00 PM, Courtney Cavin wrote:
On Wed, Nov 06, 2013 at 04:56:45PM +0100, Georgi Djakov wrote:
This platform driver adds the initial support of Secure
Digital Host Controller Interface compliant controller
found in Qualcomm MSM chipsets.
On Thu, 2014-01-30 at 17:13 +, Marc Zyngier wrote:
Hi Ian,
On 30/01/14 16:11, Ian Campbell wrote:
mach-virt has existed for a while but it is not written down what it
actually
consists of. Although it seems a bit unusual to document a binding for an
entire platform since mach-virt
On 30/01/14 17:21, Ian Campbell wrote:
On Thu, 2014-01-30 at 17:13 +, Marc Zyngier wrote:
Hi Ian,
On 30/01/14 16:11, Ian Campbell wrote:
mach-virt has existed for a while but it is not written down what it
actually
consists of. Although it seems a bit unusual to document a binding for
On Thu, 2014-01-30 at 17:24 +, Marc Zyngier wrote:
I'm afraid I disagree with most of the above. The whole point of
mach-virt is to provide a shell for DT platforms. None of this hardware
is mandated. Instead, all the necessary information should be described
in DT.
Add support
On 30/01/14 17:28, Arnd Bergmann wrote:
On Thursday 30 January 2014, Ian Campbell wrote:
mach-virt has existed for a while but it is not written down what it actually
consists of. Although it seems a bit unusual to document a binding for an
entire platform since mach-virt is entirely virtual
On Thu, 2014-01-30 at 18:28 +0100, Arnd Bergmann wrote:
On Thursday 30 January 2014, Ian Campbell wrote:
mach-virt has existed for a while but it is not written down what it
actually
consists of. Although it seems a bit unusual to document a binding for an
entire platform since mach-virt
Hi Ian,
On 01/30/2014 12:15 PM, Ian Campbell wrote:
On Thu, 2014-01-30 at 11:54 -0500, Christopher Covington wrote:
+++ b/Documentation/devicetree/bindings/arm/mach-virt.txt
@@ -0,0 +1,32 @@
+* Mach-virt Dummy Virtual Machine platform
+
+mach-virt is the smallest, dumbest platform possible,
On Wed, Jan 29, 2014 at 12:26:35PM -0500, Suravee Suthikulanit wrote:
On 1/29/2014 11:16 AM, Andreas Herrmann wrote:
On Wed, Jan 29, 2014 at 11:59:12AM -0500, Suravee Suthikulanit wrote:
On 1/29/2014 10:57 AM, Rob Herring wrote:
diff --git a/include/linux/of.h b/include/linux/of.h
index
On Thu, Jan 30, 2014 at 7:21 AM, Arnd Bergmann a...@arndb.de wrote:
On Thursday 30 January 2014, Tanmay Inamdar wrote:
When you repost, please make sure you fix whatever problem is
preventing your email from appearing on the vger mailing lists. I
won't apply things that haven't appeared
At late init all unused clocks are disabled. So clocks that were not
get before will be gated. In Keysone 2 SoC we have at least one
necessary clock that is not used by any driver - msmcsram. This
clock is necessary, because it supplies the Multicore Shared Memory
Controller (MSMC). MSMC is the
Pull the SoC device tree bits into their own files so other boards based
on these SoCs can include them and reduce duplication across a number of
boards.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8660-surf.dts | 59 +--
On Tue, Jan 28, 2014 at 01:39:12AM +0100, Sebastian Hesselbarth wrote:
This patch set is one required step for Dove to hop into mach-mvebu.
Until now, pinctrl-dove was hardcoding some registers that do not
directly belong to MPP core registers. This is not compatible with
what we want for
On Thursday 30 January 2014, Patrice CHOTARD wrote:
From: Alexandre TORGUE alexandre.tor...@st.com
This patch adds support to STiD127 SoC.
The main adaptation is the L2 cache way size compare to STiH41x SoCs.
Signed-off-by: alexandre torgue alexandre.tor...@st.com
Signed-off-by: Patrice
This patchset adds basic support of the Secure Digital Host Controller
Interface compliant controller found in Qualcomm chipsets.
Tested with eMMC and various micro SD cards on APQ8074 Dragonboard.
Changes from v7:
- Added call to sdhci_get_of_property().
- Refactored
This patch adds the device-tree binding documentation for
Qualcomm SDHCI driver. It contains the differences between
the core properties in mmc.txt and the properties used by
the sdhci-msm driver.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
---
.../devicetree/bindings/mmc/sdhci-msm.txt
This patch adds implementation for platform specific tuning in order to support
HS200 bus speed mode on Qualcomm SDHCI controller.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
---
drivers/mmc/host/sdhci-msm.c | 417 +-
1 file changed, 412
This platform driver adds the initial support of Secure
Digital Host Controller Interface compliant controller
found in Qualcomm chipsets.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
---
drivers/mmc/host/Kconfig | 13 ++
drivers/mmc/host/Makefile|1 +
On Thursday 30 January 2014, Arnd Bergmann wrote:
On Thursday 30 January 2014, Patrice CHOTARD wrote:
From: Alexandre TORGUE alexandre.tor...@st.com
This patch adds support to STiD127 SoC.
The main adaptation is the L2 cache way size compare to STiH41x SoCs.
Signed-off-by: alexandre
On 01/30/2014 07:29 PM, Andrew Lunn wrote:
On Tue, Jan 28, 2014 at 01:39:12AM +0100, Sebastian Hesselbarth wrote:
This patch set is one required step for Dove to hop into mach-mvebu.
Until now, pinctrl-dove was hardcoding some registers that do not
directly belong to MPP core registers. This is
On Thu, Dec 12, 2013 at 3:08 AM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
Second: The interrupt is registered as GIC 37, which is a real interrupt on
the Socfpga. I would expect it to be marked as GPIO 2xx (or something in
that
range). The interrupt from the gpiochip itself isn't
Hi Tejun,
As it had being awhile, any issue with this version of the SATA
drivers before I post the follow on errata patches?
-Loc
On Thu, Jan 16, 2014 at 8:11 AM, Loc Ho l...@apm.com wrote:
This patch adds support for the APM X-Gene SoC SATA host controller. In
order for the host controller
On Thu, Jan 30, 2014 at 07:50:34PM +0100, Sebastian Hesselbarth wrote:
On 01/30/2014 07:29 PM, Andrew Lunn wrote:
On Tue, Jan 28, 2014 at 01:39:12AM +0100, Sebastian Hesselbarth wrote:
This patch set is one required step for Dove to hop into mach-mvebu.
Until now, pinctrl-dove was hardcoding
Hi Tim,
On Thu, Jan 30, 2014 at 01:11:18AM -0800, Tim Harvey wrote:
My approach has been to define a per-baseboard device-tree in Linux
for a 'fully loaded' board, then remove nodes which the EEPROM claims
are not present in the bootloader before it passes the DTB to the
kernel. I do this by
Hi!
On Thu, Jan 30, 2014 at 01:40:04PM -0600, delicious quinoa wrote:
On Thu, Dec 12, 2013 at 3:08 AM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
Second: The interrupt is registered as GIC 37, which is a real interrupt
on
the Socfpga. I would expect it to be marked as GPIO 2xx
Ezequiel,
On Wed, Jan 29, 2014 at 03:19:50PM -0300, Ezequiel Garcia wrote:
On Mon, Jan 27, 2014 at 12:27:00PM -0300, Ezequiel Garcia wrote:
A new round, mostly fixing some minor nitpicks.
If anyone wants to give this a test, here's a public branch:
On Thu, Jan 30, 2014 at 03:45:58PM -0500, Jason Cooper wrote:
This is more of a process question: Is there any information captured
in your EEPROM that can't be represented in the dtb? iow, at the point
when you write the EEPROM, why not write the dtb to it as configured?
I can share what
On Thu, Jan 30, 2014 at 2:50 PM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
Hi!
On Thu, Jan 30, 2014 at 01:40:04PM -0600, delicious quinoa wrote:
On Thu, Dec 12, 2013 at 3:08 AM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
Second: The interrupt is registered as GIC 37, which
On Thu, Jan 30, 2014 at 03:15:11PM -0600, delicious quinoa wrote:
On Thu, Jan 30, 2014 at 2:50 PM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
Hi!
On Thu, Jan 30, 2014 at 01:40:04PM -0600, delicious quinoa wrote:
On Thu, Dec 12, 2013 at 3:08 AM, Steffen Trumtrar
On Sun, Jan 19, 2014 at 07:56:52PM -0800, Olof Johansson wrote:
This is a small series enhancing the MMC core code to power on modules
before the host in cases where needed, and the corresponding DT bindings
changes.
I've got some other issues to debug on the Chromebook, i.e. the interface
On Thu, Jan 30, 2014 at 03:53:15PM -0500, Jason Cooper wrote:
Ezequiel,
On Wed, Jan 29, 2014 at 03:19:50PM -0300, Ezequiel Garcia wrote:
On Mon, Jan 27, 2014 at 12:27:00PM -0300, Ezequiel Garcia wrote:
A new round, mostly fixing some minor nitpicks.
If anyone wants to give this a
Hello.
On 01/29/2014 07:16 PM, Rob Herring wrote:
This patch is an attempt to gather the Ethernet related bindings in one
file,
like it's done in the MMC and some other subsystems. It should save some
of
the trouble of documenting several properties over and over in each
binding
document,
On 01/30/2014 10:50 PM, Ezequiel Garcia wrote:
On Thu, Jan 30, 2014 at 03:53:15PM -0500, Jason Cooper wrote:
Ezequiel,
On Wed, Jan 29, 2014 at 03:19:50PM -0300, Ezequiel Garcia wrote:
On Mon, Jan 27, 2014 at 12:27:00PM -0300, Ezequiel Garcia wrote:
A new round, mostly fixing some minor
On Thu, Jan 30, 2014 at 3:32 PM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
On Thu, Jan 30, 2014 at 03:15:11PM -0600, delicious quinoa wrote:
On Thu, Jan 30, 2014 at 2:50 PM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
Hi!
On Thu, Jan 30, 2014 at 01:40:04PM -0600, delicious
On Thu, Jan 30, 2014 at 11:00:50PM +0100, Sebastian Hesselbarth wrote:
On 01/30/2014 10:50 PM, Ezequiel Garcia wrote:
On Thu, Jan 30, 2014 at 03:53:15PM -0500, Jason Cooper wrote:
Ezequiel,
On Wed, Jan 29, 2014 at 03:19:50PM -0300, Ezequiel Garcia wrote:
On Mon, Jan 27, 2014 at 12:27:00PM
On Thu, Jan 30, 2014 at 11:00:50PM +0100, Sebastian Hesselbarth wrote:
On 01/30/2014 10:50 PM, Ezequiel Garcia wrote:
On Thu, Jan 30, 2014 at 03:53:15PM -0500, Jason Cooper wrote:
Ezequiel,
On Wed, Jan 29, 2014 at 03:19:50PM -0300, Ezequiel Garcia wrote:
On Mon, Jan 27, 2014 at
On 1/29/2014 12:03 PM, Will Deacon wrote:
On Wed, Jan 29, 2014 at 05:57:16PM +, Suravee Suthikulanit wrote:
On 1/29/2014 11:29 AM, Will Deacon wrote:
On Wed, Jan 29, 2014 at 05:26:35PM +, Suravee Suthikulanit wrote:
On 1/29/2014 11:16 AM, Andreas Herrmann wrote:
On Wed, Jan 29, 2014
On IBM pseries systems the device_type device-tree property of a PCIe
bridge contains the string pciex. The of_bus_pci_match() function was
looking only for pci on this property, so in such cases the bus
matching code was falling back to the default bus, causing problems on
functions that should
On Wed, Jan 29, 2014 at 5:32 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Wed, Jan 29, 2014 at 12:25:20PM +, Mark Brown wrote:
On Wed, Jan 29, 2014 at 12:10:48PM +0100, Maxime Ripard wrote:
+config SPI_SUN6I
+ tristate Allwinner A31 SPI controller
+ depends on
On Thu, Jan 30, 2014 at 10:53:35PM +, Suravee Suthikulanit wrote:
On 1/29/2014 12:03 PM, Will Deacon wrote:
Interesting... how does that work for PCI? Do you force all devices behind a
given RC into the same address space?
For PCI devices, we are using the bus, device, and function
Hi Sudeep,
On 01/30/2014 07:43 AM, Sudeep Holla wrote:
I am looking into a couple shortcomings in the current OPP bindings and
how to address them. Feel free to add to the list if you think of any more
issues that needs to be addressed or if and how any problem mentioned below
can be
On 01/30/2014 09:25 PM, Andrew Lunn wrote:
On Thu, Jan 30, 2014 at 07:50:34PM +0100, Sebastian Hesselbarth wrote:
On 01/30/2014 07:29 PM, Andrew Lunn wrote:
On Tue, Jan 28, 2014 at 01:39:12AM +0100, Sebastian Hesselbarth wrote:
This patch set is one required step for Dove to hop into
On Thu, Jan 30, 2014 at 12:45 PM, Jason Cooper ja...@lakedaemon.net wrote:
Hi Tim,
On Thu, Jan 30, 2014 at 01:11:18AM -0800, Tim Harvey wrote:
My approach has been to define a per-baseboard device-tree in Linux
for a 'fully loaded' board, then remove nodes which the EEPROM claims
are not
On Thu, Jan 30, 2014 at 1:15 PM, Jason Gunthorpe
jguntho...@obsidianresearch.com wrote:
On Thu, Jan 30, 2014 at 03:45:58PM -0500, Jason Cooper wrote:
This is more of a process question: Is there any information captured
in your EEPROM that can't be represented in the dtb? iow, at the
Hi Tomasz,
Thanks for the review.
Will consider all your comments in the next version of patch series.
Regards,
Shaik Ameer Basha
On Sat, Jan 25, 2014 at 1:09 AM, Tomasz Figa t.f...@samsung.com wrote:
Hi Shaik,
On 09.01.2014 04:28, Shaik Ameer Basha wrote:
This patch adds the DT binding
Hi Vinod,
On Tue, Jan 28, 2014 at 8:43 AM, Vinod Koul vinod.k...@intel.com wrote:
On Mon, Jan 27, 2014 at 06:42:36PM +0530, Srikanth Thokala wrote:
Hi Lars/Vinod,
The question here i think would be waht this device supports? Is the
hardware
capable of doing interleaved transfers, then
Hi Vinod,
On Mon, Jan 27, 2014 at 4:36 PM, Srikanth Thokala stho...@xilinx.com wrote:
Hi Vinod,
On Sun, Jan 26, 2014 at 7:29 PM, Vinod Koul vinod.k...@intel.com wrote:
On Fri, Jan 24, 2014 at 02:24:27PM +0100, Lars-Peter Clausen wrote:
On 01/24/2014 12:16 PM, Srikanth Thokala wrote:
Hi
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