On Tue, Feb 04, 2014 at 07:19:07AM -0500, Matt Porter wrote:
Voltage regulators are needed very early due to deferred probe
being incompatible with built-in USB gadget drivers.
What does it need to fix those instead?
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Hi Srinivas,
Am Montag, den 03.02.2014, 14:27 + schrieb
srinivas.kandaga...@st.com:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
Hi All,
This patch series adds reset controller support for STi SOC series STiH415 and
STiH416. It adds support for both power down reset and soft
On Wednesday 05 February 2014, Michal Simek wrote:
I am not quite sure what you mean by reports to user space.
If you mean to get timeout through ioctl for example - then yes it is working
through standard watchdog ioctl interface and timeout is calculated
from hardware setup.
Yes, that is
On 02/05/2014 10:36 AM, Arnd Bergmann wrote:
On Wednesday 05 February 2014, Michal Simek wrote:
I am not quite sure what you mean by reports to user space.
If you mean to get timeout through ioctl for example - then yes it is working
through standard watchdog ioctl interface and timeout is
On Tue, 4 Feb 2014 12:39:41 -0800, Florian Fainelli f.faine...@gmail.com
wrote:
2014-01-17 Matthew Garrett matthew.garr...@nebula.com:
Some hardware may be broken in interesting and board-specific ways, such
that various bits of functionality don't work. This patch provides a
mechanism for
From: Florian Fainelli
It would be good to explain exactly how your hardware is broken
exactly. I really do not think that such a fine-grained setting where
you could disable, e.g: 100BaseT_Full, but allow 100BaseT_Half to
remain usable makes that much sense. In general, Gigabit might be
On Tue, 04 Feb 2014 13:09:33 +0100, Marek Szyprowski m.szyprow...@samsung.com
wrote:
From: Grant Likely grant.lik...@linaro.org
Reserved memory nodes allow for the reservation of static (fixed
address) regions, or dynamically allocated regions for a specific
purpose.
[joshc: Based on
On Tue, 04 Feb 2014 13:09:32 +0100, Marek Szyprowski m.szyprow...@samsung.com
wrote:
Enable reserved memory initialization from device tree.
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Laura Abbott lau...@codeaurora.org
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
On Tue, Feb 4, 2014 at 11:24 PM, Jonathan Cameron ji...@kernel.org wrote:
On February 5, 2014 4:43:35 AM GMT+00:00, Matt Porter mpor...@linaro.org
wrote:
On Tue, Feb 04, 2014 at 07:14:55PM -0800, Matt Ranostay Matt Ranostay
wrote:
Document compatible string, required and optional DT
Please ignore my comment.
I will try to use exported tegra_fuse_readl().
-Original Message-
From: Peter De Schrijver [mailto:pdeschrij...@nvidia.com]
Sent: Monday, February 03, 2014 10:15 PM
To: Jim Lin
Cc: linux-arm-ker...@lists.infradead.org; linux-te...@vger.kernel.org;
Hi Srinivas
Thanks for reviewing, a V2 serie will be pushed with all required fixes.
Patrice
On 01/31/2014 01:50 PM, srinivas kandagatla wrote:
Hi Patrice,
On 30/01/14 14:55, Patrice CHOTARD wrote:
From: Alexandre TORGUE alexandre.tor...@st.com
The STid127 integrates all harware components
On Wed, Feb 05, 2014 at 12:43:18PM +0800, Chen-Yu Tsai wrote:
On Tue, Feb 4, 2014 at 3:38 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Mon, Feb 03, 2014 at 11:32:26AM +0800, Chen-Yu Tsai wrote:
U-Boot will insert MAC address into the device tree image.
It looks up
Hi David,
On Tue, Feb 04, 2014 at 08:24:13PM +0100, David Lanzendörfer wrote:
Hello
The following patchset adds support for the SD/MMC host found in the
Allwinner SoCs.
It contains all the necessary modifications for clock environment and also
the device
tree script modification which add
On February 5, 2014 10:22:24 AM GMT+00:00, Matt Ranostay mranos...@gmail.com
wrote:
On Tue, Feb 4, 2014 at 11:24 PM, Jonathan Cameron ji...@kernel.org
wrote:
On February 5, 2014 4:43:35 AM GMT+00:00, Matt Porter
mpor...@linaro.org wrote:
On Tue, Feb 04, 2014 at 07:14:55PM -0800, Matt
On Tue, 04 Feb 2014 13:09:29 +0100, Marek Szyprowski m.szyprow...@samsung.com
wrote:
This patch adds device tree support for contiguous and reserved memory
regions defined in device tree.
Large memory blocks can be reliably reserved only during early boot.
This must happen before the whole
On Tue, 04 Feb 2014 13:09:31 +0100, Marek Szyprowski m.szyprow...@samsung.com
wrote:
From: Josh Cartwright jo...@codeaurora.org
Add support for handling 'shared-dma-pool' reserved-memory nodes using
Contiguous Memory Allocator driver.
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
On Wed, 29 Jan 2014 14:53:32 -0300, Ezequiel Garcia
ezequiel.gar...@free-electrons.com wrote:
On Wed, Jan 29, 2014 at 03:34:13PM +0100, Boris BREZILLON wrote:
nand-ecc-level property statically defines NAND chip's ECC requirements.
Signed-off-by: Boris BREZILLON b.brezillon@gmail.com
Hi Arnd,
On 31/01/14 20:15, Arnd Bergmann wrote:
On Friday 31 January 2014, srinivas kandagatla wrote:
Sorry if I missed the initial review, but can you explain
why this is needed to start with?
On ST SoCs the default value for L2 AUX_CTRL register is 0x0, so we set
the way-size explicit
Am Mittwoch, 5. Februar 2014, 11:12:47 schrieb Grant Likely:
On Mon, 20 Jan 2014 16:42:58 +0100, Heiko Stübner he...@sntech.de wrote:
Some SoCs need parts of their sram for special purposes. So while being
part of the peripheral, it should not be part of the genpool controlling
the sram.
On Tue, 04 Feb 2014 21:40:16 +0300, Sergei Shtylyov
sergei.shtyl...@cogentembedded.com wrote:
Hello.
On 02/04/2014 08:26 PM, Grant Likely wrote:
I'm afraid that's too late, it has spread very far, so that
of_get_phy_mode() handles that property, not phy-connection-type.
Uggg, I
Am Mittwoch, 5. Februar 2014, 12:06:52 schrieb Grant Likely:
On Tue, 04 Feb 2014 19:48:17 +0100, Heiko Stübner he...@sntech.de wrote:
Hi Grant,
On Tuesday, 4. February 2014 17:30:34 Grant Likely wrote:
On Sat, 18 Jan 2014 09:07:30 -0600, Rob Herring robherri...@gmail.com
wrote:
and corrected patches.
Looking forward for the next iteration!
Good :-)
You can have a look at the recent status here:
http://git.o2s.ch/?p=linux-next.git;a=shortlog;h=refs/heads/20140205
cheers
David
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Hi everyone,
This patchset brings support for the SPI controller found in the
Allwinner A31 SoC.
Even though the controller supports DMA, the driver only supports PIO
mode for now. This driver will be used to bring up and test DMA on the
SoC, so support for the DMA will come eventually.
It
The A31 has 4 SPI controllers. Add them in the DTSI.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 40
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi
The Allwinner A31 has a new SPI controller IP compared to the older Allwinner
SoCs.
It supports DMA, but the driver only does PIO for now, and DMA will be
supported eventually.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
.../devicetree/bindings/spi/spi-sun6i.txt |
The module clocks in the A31 are still compatible with the A10 one. Add the SPI
module clocks and the PLL6 in the device tree to allow their use by the SPI
controllers.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 46
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/configs/sunxi_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 3e2259b..b5df4a5 100644
--- a/arch/arm/configs/sunxi_defconfig
+++
On Tuesday 04 February 2014 09:44 PM, Thomas Gleixner wrote:
On Mon, 3 Feb 2014, Sricharan R wrote:
I already have your reviewed-by tag for the first patch in this series.
Kevin was pointing out that irqchip maintainer tag is needed for this patch
as well
to be merged. We are planning to
Hi
I'm not that fond of these default y patterns. It forces the driver
down to every user of the multiplatform kernels. I'd suggest removing
the default and adding the driver to the defconfigs we have.
Ok. Removed it.
+static void sunxi_mmc_init_host(struct mmc_host *mmc)
+{
[...]
+
On 05/02/2014 12:15, Grant Likely wrote:
On Wed, 29 Jan 2014 14:53:32 -0300, Ezequiel Garcia
ezequiel.gar...@free-electrons.com wrote:
On Wed, Jan 29, 2014 at 03:34:13PM +0100, Boris BREZILLON wrote:
nand-ecc-level property statically defines NAND chip's ECC requirements.
Signed-off-by:
Add a broadcast timer64 based clockevent driver for keystone arch.
This driver uses timer in 64-bit general purpose mode as clock event
device.
Documentation:
http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
Based on
git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git
Add broadcast clock-event device for the Keystone arch.
The timer can be configured as a general-purpose 64-bit timer,
dual general-purpose 32-bit timers. When configured as dual 32-bit
timers, each half can operate in conjunction (chain mode) or
independently (unchained mode) of each other.
Add keystone timer entry to keystone device tree.
This 64-bit timer is used as backup clock event device.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/boot/dts/keystone-clocks.dtsi | 10 ++
arch/arm/boot/dts/keystone.dtsi| 7 +++
2 files changed, 17
This patch provides bindings for the 64-bit timer in the KeyStone
architecture devices. The timer can be configured as a general-purpose 64-bit
timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
timers, each half can operate in conjunction (chain mode) or independently
From: Jack Mitchell j...@embed.me.uk
Devicetree include file for setting up the am335x mcasp bus, i2c-2
bus, and audio codec required for a functioning BeagleBone Audio Cape.
Signed-off-by: Jack Mitchell j...@embed.me.uk
Signed-off-by: Matt Porter mpor...@linaro.org
---
From: Emilio López emi...@elopez.com.ar
This commit implements .determine_rate, so that our factor clocks can be
reparented when needed.
Signed-off-by: Emilio López emi...@elopez.com.ar
---
drivers/clk/sunxi/clk-factors.c | 36
1 file changed, 36
Hello
The following patchset adds support for the SD/MMC host found in the Allwinner
SoCs.
It contains all the necessary modifications for clock environment and also the
device
tree script modification which add it to all the boards using it.
The clock environment function needed for phase
From: Hans de Goede hdego...@redhat.com
Signed-off-by: Hans de Goede hdego...@redhat.com
---
include/linux/clk/sunxi.h | 22 ++
1 file changed, 22 insertions(+)
create mode 100644 include/linux/clk/sunxi.h
diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
Signed-off-by: David Lanzendörfer david.lanzendoer...@o2s.ch
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 30 +++
arch/arm/boot/dts/sun5i-a10s.dtsi| 44 ++
Signed-off-by: David Lanzendörfer david.lanzendoer...@o2s.ch
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun4i-a10-a1000.dts |8
arch/arm/boot/dts/sun4i-a10-cubieboard.dts |8
arch/arm/boot/dts/sun4i-a10.dtsi | 54
This is based on the driver Allwinner ships in their Android kernel sources.
Initial porting to upstream kernels done by David Lanzendörfer, additional
fixes and cleanups by Hans de Goede.
It uses dma in bus-master mode using a built-in designware idmac controller,
which is identical to the one
From: Emilio López emi...@elopez.com.ar
Signed-off-by: Emilio López emi...@elopez.com.ar
---
drivers/clk/sunxi/clk-sunxi.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index
Signed-off-by: David Lanzendörfer david.lanzendoer...@o2s.ch
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts |8 +++
arch/arm/boot/dts/sun7i-a20-cubietruck.dts |8 +++
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 23
On Wednesday 05 February 2014, Michal Simek wrote:
On 02/05/2014 10:36 AM, Arnd Bergmann wrote:
On Wednesday 05 February 2014, Michal Simek wrote:
Still, the choice of putting the timeout into DT in terms of
cycles rather than miliseconds wasn't ideal from an interface
perspective and we
Hello Brian,
On 23/01/2014 02:49, Brian Norris wrote:
+ Huang
Hi Boris,
On Wed, Jan 08, 2014 at 03:21:56PM +0100, Boris BREZILLON wrote:
The Hynix nand flashes store their ECC requirements in byte 4 of its id
(returned on READ ID command).
Signed-off-by: Boris BREZILLON
On Tuesday 04 February 2014 08:48 PM, Nishanth Menon wrote:
On 02/04/2014 06:44 AM, Balaji T K wrote:
On Tuesday 21 January 2014 04:59 AM, Nishanth Menon wrote:
When device is booted using devicetree, platforms impacted by
Erratum 2.1.1.128 is not detected easily in the mmc driver. This
Tony,
On Wednesday 05 February 2014 06:41 PM, Sricharan R wrote:
On Tuesday 04 February 2014 09:44 PM, Thomas Gleixner wrote:
On Mon, 3 Feb 2014, Sricharan R wrote:
I already have your reviewed-by tag for the first patch in this series.
Kevin was pointing out that irqchip maintainer tag is
On 02/05/2014 07:48 AM, Jack Mitchell wrote:
From: Jack Mitchell j...@embed.me.uk
Devicetree include file for setting up the am335x mcasp bus, i2c-2
bus, and audio codec required for a functioning BeagleBone Audio Cape.
Signed-off-by: Jack Mitchell j...@embed.me.uk
Signed-off-by: Matt
On Wed 05 Feb 2014 08:10:34 AM CST, Balaji T K wrote:
On Tuesday 04 February 2014 08:48 PM, Nishanth Menon wrote:
On 02/04/2014 06:44 AM, Balaji T K wrote:
On Tuesday 21 January 2014 04:59 AM, Nishanth Menon wrote:
When device is booted using devicetree, platforms impacted by
Erratum
Hello.
On 02/05/2014 03:08 PM, Grant Likely wrote:
I'm afraid that's too late, it has spread very far, so that
of_get_phy_mode() handles that property, not phy-connection-type.
Uggg, I guess this is a case of a defacto standard then if the kernel
doesn't even support it.
Maybe I
On Wed, Feb 05, 2014 at 08:09:16AM -0600, Nishanth Menon wrote:
On 02/05/2014 07:48 AM, Jack Mitchell wrote:
From: Jack Mitchell j...@embed.me.uk
Devicetree include file for setting up the am335x mcasp bus, i2c-2
bus, and audio codec required for a functioning BeagleBone Audio Cape.
On Wed, Feb 5, 2014 at 7:47 AM, Ivan Khoronzhuk ivan.khoronz...@ti.com wrote:
This patch provides bindings for the 64-bit timer in the KeyStone
architecture devices. The timer can be configured as a general-purpose 64-bit
timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
The similar GPIO HW block is used by keystone SoCs as
in Davinci SoCs.
Hence, reuse Davinci GPIO driver for Keystone taking into
account that Keystone contains ARM GIC IRQ controller which
is implemented using IRQ Chip.
Documentation:
http://www.ti.com/lit/ug/sprugv1/sprugv1.pdf
Quoting Maxime Ripard (2014-02-05 05:05:03)
The A31 has a slightly different PLL6 clock. Add support for this new clock in
our driver.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Looks good to me.
Regards,
Mike
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1
On 02/05/2014 08:38 AM, Matt Porter wrote:
On Wed, Feb 05, 2014 at 08:09:16AM -0600, Nishanth Menon wrote:
On 02/05/2014 07:48 AM, Jack Mitchell wrote:
[...]
+ * --- a/arch/arm/boot/dts/am335x-boneblack.dts
+ * +++ b/arch/arm/boot/dts/am335x-boneblack.dts
+ * @@ -73,6 +74,6 @@
+ *
On Wed, Feb 05, 2014 at 02:05:05PM +0100, Maxime Ripard wrote:
The Allwinner A31 has a new SPI controller IP compared to the older Allwinner
SoCs.
Looks good - applied, thanks!
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On Wed, Feb 05, 2014 at 10:08:18AM +0100, Wolfram Sang wrote:
On Tue, Feb 04, 2014 at 07:19:07AM -0500, Matt Porter wrote:
Voltage regulators are needed very early due to deferred probe
being incompatible with built-in USB gadget drivers.
What does it need to fix those instead?
[added
Add a new driver for the ARM CLPS711X Pulse Width Modulator (PWM) interface.
This CPU contain two 4-bit PWM outputs with constant period, based on CPU
PLL frequency. PWM polarity is determined by hardware by power on reset.
Signed-off-by: Alexander Shiyan shc_w...@mail.ru
---
On Wed, Feb 05, 2014 at 08:56:34AM -0600, Nishanth Menon wrote:
On 02/05/2014 08:38 AM, Matt Porter wrote:
On Wed, Feb 05, 2014 at 08:09:16AM -0600, Nishanth Menon wrote:
On 02/05/2014 07:48 AM, Jack Mitchell wrote:
[...]
+ * --- a/arch/arm/boot/dts/am335x-boneblack.dts
+ * +++
On Wed, 5 Feb 2014, Matt Porter wrote:
On Wed, Feb 05, 2014 at 10:08:18AM +0100, Wolfram Sang wrote:
On Tue, Feb 04, 2014 at 07:19:07AM -0500, Matt Porter wrote:
Voltage regulators are needed very early due to deferred probe
being incompatible with built-in USB gadget drivers.
Hi,
I would like to get some comments on logiCVC video controller binding from
patch.
Thank you,
Davor
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Xylon binding of DRM driver and logiCVC IP core.
Signed-off-by: Davor Joja davorj...@logicbricks.com
---
.../devicetree/bindings/drm/xylon/logicvc.txt | 79
.../devicetree/bindings/drm/xylon/xylon_drm.txt| 24 ++
2 files changed, 103 insertions(+)
create
Hi David,
On 02/05/2014 02:01 PM, David Lanzendörfer wrote:
Hi Maxime
I have four comments here:
- Read Documentation/SubmittingPatches, especially Section 5 and 12
(hints, you forgot the clock maintainers for your clock patches
and you didn't put any signed-off-by tags)
Oops. I
Hi Olof,
From: Olof Johansson [mailto:o...@lixom.net]
Sent: Wednesday, January 29, 2014 9:51 PM
On Wed, Jan 29, 2014 at 9:29 AM, Kamil Debski k.deb...@samsung.com
wrote:
Add support to PHY of USB2 of the Exynos 4 SoC.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
Quoting Dinh Nguyen (2014-01-15 04:36:52)
Hi Mike,
Can you apply this to your clk tree?
The patch looks good to me, but I think it depends on your pending pull
request. Can you add this to that pull request and rebase it to
3.14-rc1?
Thanks,
Mike
Thanks,
Dinh
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Hi Olof,
Thank you for your review.
From: Olof Johansson [mailto:o...@lixom.net]
Sent: Wednesday, January 29, 2014 9:55 PM
Hi,
On Wed, Jan 29, 2014 at 9:29 AM, Kamil Debski k.deb...@samsung.com
wrote:
Change the phy provider used from the old one using the USB phy
framework to a new
Hi Alan,
Thank you for your review.
From: Alan Stern [mailto:st...@rowland.harvard.edu]
Sent: Wednesday, January 29, 2014 9:43 PM
On Wed, 29 Jan 2014, Kamil Debski wrote:
Change the phy provider used from the old one using the USB phy
framework to a new one using the Generic phy
On Thu, 30 Jan 2014 14:54:36 +0100
Linus Walleij linus.wall...@linaro.org wrote:
On Mon, Jan 13, 2014 at 5:56 PM, Alexander Shiyan shc_w...@mail.ru wrote:
SYSCON driver was designed for using memory areas (registers)
that are used in several subsystems. There are systems (CPUs)
which use
On Fri, Jan 31, 2014 at 12:21 PM, Srikanth Thokala stho...@xilinx.com wrote:
Hi Vinod,
On Tue, Jan 28, 2014 at 8:43 AM, Vinod Koul vinod.k...@intel.com wrote:
On Mon, Jan 27, 2014 at 06:42:36PM +0530, Srikanth Thokala wrote:
Hi Lars/Vinod,
The question here i think would be waht this device
On 02/05/2014 04:39 PM, Rob Herring wrote:
On Wed, Feb 5, 2014 at 7:47 AM, Ivan Khoronzhuk ivan.khoronz...@ti.com wrote:
This patch provides bindings for the 64-bit timer in the KeyStone
architecture devices. The timer can be configured as a general-purpose 64-bit
timer, dual general-purpose
On Wed, Feb 05, 2014 at 10:30:29AM -0500, Alan Stern wrote:
On Wed, 5 Feb 2014, Matt Porter wrote:
On Wed, Feb 05, 2014 at 10:08:18AM +0100, Wolfram Sang wrote:
On Tue, Feb 04, 2014 at 07:19:07AM -0500, Matt Porter wrote:
Voltage regulators are needed very early due to deferred
On 02/05/2014 05:25 PM, Srikanth Thokala wrote:
On Fri, Jan 31, 2014 at 12:21 PM, Srikanth Thokala stho...@xilinx.com wrote:
Hi Vinod,
On Tue, Jan 28, 2014 at 8:43 AM, Vinod Koul vinod.k...@intel.com wrote:
On Mon, Jan 27, 2014 at 06:42:36PM +0530, Srikanth Thokala wrote:
Hi Lars/Vinod,
The
Parse the device tree node to populate platform data.
Cc: devicetree@vger.kernel.org
Signed-off-by: Laurent Pinchart laurent.pinch...@ideasonboard.com
---
.../devicetree/bindings/media/i2c/adv7604.txt | 56
drivers/media/i2c/adv7604.c| 101
On Fri, Jan 17, 2014 at 11:44:23AM +0100, Andrew Lunn wrote:
I've not looked at regulators, but i would hope it also does reference
counting of a regulators users.
Yes, it does.
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As Maxime has pointed out, I've forgotten to add a changelog
in my coverletter.
Here is, what has changed in this revision:
Changes since v1:
-Using mmc_of_parse instead of diy dt parsing
-Adding nodes for all mmc controller to the dtsi files, including sofar unused
controllers
-Using generic
On Wed, 2014-02-05 at 08:03 -0800, Mike Turquette wrote:
Quoting Dinh Nguyen (2014-01-15 04:36:52)
Hi Mike,
Can you apply this to your clk tree?
The patch looks good to me, but I think it depends on your pending pull
request. Can you add this to that pull request and rebase it to
Using platform_get_irq_byname() to retrieve the IRQ number
returns the VIRQ number rather than the local IRQ number for
the device. Passing that value then into regmap_irq_get_virq()
causes a failure because the function is expecting the local
IRQ number (e.g. 0, 1, 2, 3, etc). This patch removes
Signed-off-by: Adam Thomson adam.thomson.opensou...@diasemi.com
---
Documentation/devicetree/bindings/sound/da9055.txt | 22
sound/soc/codecs/da9055.c |8 +++
2 files changed, 30 insertions(+), 0 deletions(-)
create mode 100644
This patch series provides the following updates for DA9055 drivers:
- Fixes an issue with da9055 driver initialisation (conflicting device ids) of
PMIC (MFD) and CODEC drivers.
- Add initial DT support for DA9055 related drivers, including binding
documentation.
- Remove conflicting use
Signed-off-by: Adam Thomson adam.thomson.opensou...@diasemi.com
---
drivers/regulator/da9055-regulator.c | 59 +++---
1 files changed, 54 insertions(+), 5 deletions(-)
diff --git a/drivers/regulator/da9055-regulator.c
b/drivers/regulator/da9055-regulator.c
index
Signed-off-by: Adam Thomson adam.thomson.opensou...@diasemi.com
---
Documentation/devicetree/bindings/mfd/da9055.txt | 73 ++
drivers/mfd/da9055-i2c.c |8 +++
2 files changed, 81 insertions(+), 0 deletions(-)
create mode 100644
Signed-off-by: Adam Thomson adam.thomson.opensou...@diasemi.com
---
drivers/mfd/da9055-core.c | 46 -
1 files changed, 0 insertions(+), 46 deletions(-)
diff --git a/drivers/mfd/da9055-core.c b/drivers/mfd/da9055-core.c
index caf8dcf..5cf8ca6 100644
Signed-off-by: Adam Thomson adam.thomson.opensou...@diasemi.com
---
drivers/rtc/rtc-da9055.c |3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/drivers/rtc/rtc-da9055.c b/drivers/rtc/rtc-da9055.c
index 48cb2ac..6e06840 100644
--- a/drivers/rtc/rtc-da9055.c
+++
On Wed, Feb 5, 2014 at 7:57 AM, Kamil Debski k.deb...@samsung.com wrote:
Hi Olof,
Thank you for your review.
From: Olof Johansson [mailto:o...@lixom.net]
Sent: Wednesday, January 29, 2014 9:55 PM
Hi,
On Wed, Jan 29, 2014 at 9:29 AM, Kamil Debski k.deb...@samsung.com
wrote:
Change the
Currently the I2C device Ids conflict for the MFD and CODEC so
cannot be both instantiated on one platform. This patch updates
the Ids and names to make them unique from each other.
It should be noted that the I2C addresses for both PMIC and CODEC
are modifiable so instantiation of the two are
On Wed, Feb 5, 2014 at 10:18 AM, Ivan Khoronzhuk ivan.khoronz...@ti.com wrote:
On 02/05/2014 04:39 PM, Rob Herring wrote:
On Wed, Feb 5, 2014 at 7:47 AM, Ivan Khoronzhuk ivan.khoronz...@ti.com
wrote:
This patch provides bindings for the 64-bit timer in the KeyStone
architecture devices.
On Wed, Feb 05, 2014 at 05:48:35PM +, Adam Thomson wrote:
+#ifdef CONFIG_OF
+#include linux/of.h
+#include linux/regulator/of_regulator.h
+#endif /* CONFIG_OF */
Don't do ifdefs for includes like this, it's not worth it.
+ for_each_child_of_node(nproot, np) {
+ if
On Wed, Feb 05, 2014 at 05:48:32PM +, Adam Thomson wrote:
Currently the I2C device Ids conflict for the MFD and CODEC so
cannot be both instantiated on one platform. This patch updates
the Ids and names to make them unique from each other.
Acked-by: Mark Brown broo...@linaro.org
On 01/28/2014 04:36 PM, Peter De Schrijver wrote:
Add efuse bindings for Tegra20, Tegra30, Tegra114 and Tegra124.
diff --git a/Documentation/devicetree/bindings/fuse/fuse-tegra.txt
b/Documentation/devicetree/bindings/fuse/fuse-tegra.txt
+- clocks: Should contain a pointer to the fuse clock.
On 02/05/2014 07:41 PM, Rob Herring wrote:
On Wed, Feb 5, 2014 at 10:18 AM, Ivan Khoronzhuk ivan.khoronz...@ti.com wrote:
On 02/05/2014 04:39 PM, Rob Herring wrote:
On Wed, Feb 5, 2014 at 7:47 AM, Ivan Khoronzhuk ivan.khoronz...@ti.com
wrote:
This patch provides bindings for the 64-bit timer
Changes since v2:
- Remove various unneeded field initialization
- Call iio_triggered_buffer_cleanup() on remove
Changes since v1:
- Rebased to 3.14-rc1
- Renamed in_pulse_polarity to pulse_polarity
- Added ABI entries for pulse devices and TI ECAP
This
Add missing interrupt properties to the ecap0, ecap1, and ecap2
nodes.
Signed-off-by: Matt Porter mpor...@linaro.org
---
arch/arm/boot/dts/am33xx.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 6d95d3d..b4139ba
Add the pulse driver subdirectory when configuring and building
IIO.
Signed-off-by: Matt Porter mpor...@linaro.org
---
drivers/iio/Kconfig | 1 +
drivers/iio/Makefile | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig
index 5dd0e12..286acc3 100644
Add a channel type to support pulse width capture devices.
These devices capture the timing of a PWM signal based on a
configurable trigger
Signed-off-by: Matt Porter mpor...@linaro.org
---
drivers/iio/industrialio-core.c | 1 +
include/linux/iio/types.h | 1 +
2 files changed, 2
Adds support for capturing PWM signals using the TI ECAP peripheral.
This driver supports triggered buffer capture of pulses on multiple
ECAP instances. In addition, the driver supports configurable polarity
of the signal to be captured.
Signed-off-by: Matt Porter mpor...@linaro.org
---
The IIO TI ECAP driver depends on the TI PWMSS management
driver in this subsystem. Enable PWMSS when the IIO TI ECAP
driver is selected.
Signed-off-by: Matt Porter mpor...@linaro.org
---
drivers/pwm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pwm/Kconfig
Daniel,
On Mon, Jan 27, 2014 at 12:27:02PM -0300, Ezequiel Garcia wrote:
Replace the driver-specific thread-safe shared register API
by the recently introduced atomic_io_clear_set().
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Tested-by: Sebastian Hesselbarth
On 01/28/2014 04:36 PM, Peter De Schrijver wrote:
Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124.
I assume most of this code is simply cut/paste from the existing code in
arch/arm/mach-tegra/? If so, git format-patch -C would have been
useful to highlight what changed when
Hello.
On 02/05/2014 10:01 PM, Matt Porter wrote:
[...]
This series adds support for PWM capture devices within IIO and
adds a TI ECAP IIO driver.
PWM capture devices are supported using a new IIO pulse channel type.
The IIO ECAP driver implements interrupt driven triggered buffer
On Wed, Feb 05, 2014 at 10:07:50AM +, Grant Likely wrote:
On Tue, 04 Feb 2014 13:09:33 +0100, Marek Szyprowski
m.szyprow...@samsung.com wrote:
From: Grant Likely grant.lik...@linaro.org
+/reserved-memory node
+-
+#address-cells, #size-cells (required) - standard
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