From: Stephen Warren swar...@nvidia.com
Implement the new DT property ti,irq-externally-inverted, and add an
equivalent platform data field to match. This allows the driver to
correctly automatically configure the IRQ output polarity when the board
or SoC contains an inverter between the
On 27/02/14 19:35, Philipp Zabel wrote:
For simple devices with only one port, it can be made implicit.
The endpoint node can be a direct child of the device node.
snip
@@ -2105,9 +2112,11 @@ struct device_node *of_graph_get_remote_port_parent(
/* Get remote endpoint node. */
np
Hi Tony,
On 03/03/2014 09:02 PM, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [140303 07:10]:
Move omap-control binding information to the right location.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 25
++
Hi,
Changes compared to v1:
- fixed OMAP2 only build issues
- fixed OMAP2420 boot issues
- added patch #13 and #14 to remove legacy clock data for OMAP2/OMAP3
- fixed smatch + DT bindings documentation problems reported by Nishanth
This set is un-tested on OMAP2 hardware as I don't have access
OMAP2 has slightly different DPLL compared to later OMAP generations.
This patch adds support for the ti,omap2-dpll-core-clock and also adds
the bindings documentation.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/dpll.txt |9 +++
This patch adds support for omap2 type aplls, which have gating and
autoidle functionality.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/apll.txt | 24 ++-
arch/arm/mach-omap2/clock.h| 11 --
drivers/clk/ti/apll.c
osc_ck can be simply defined as a multiplexer clock, and the sys_ck
can be a simple divider.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/Makefile |3 +-
arch/arm/mach-omap2/cclock2420_data.c | 52 +
ti,composite-gate-clock documentation was missing, also the register
offset examples were wrong.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/gate.txt | 29 +---
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git
Cleans up the code a bit and is useful for clock data DT conversion.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/cclock2420_data.c | 15 ---
arch/arm/mach-omap2/clock.c | 21 -
arch/arm/mach-omap2/clock.h |3 ---
AM dpll_data previously had autoidle_mask set, even if these SoC:s
don't have autoidle register. Remove the bit-field value as it is unused,
also drop the unnecessary DPLL_HAS_AUTOIDLE flag passing during init,
as we can just simply check against the contents of the autoidle_mask.
OMAP2430 I2CHS modules require specific hardware ops to be used, so added
a new compatible string for this.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/interface.txt |2 ++
arch/arm/mach-omap2/clock.h|1 -
This patch adds support for initializing also omap2-prcm and omap2-scrm
through DT.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/arm/omap/prcm.txt | 65
arch/arm/mach-omap2/prm_common.c |2 +
2 files changed, 67
Otherwise legacy boot clock data is used.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/io.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index af432b1..e57088d 100644
---
Adds support for registering the alias clocks, boot time clock-enable list
and disabling autoidle of clocks.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/ti/Makefile |1 +
drivers/clk/ti/clk-2xxx.c | 254 +
include/linux/clk/ti.h
This patch creates a unique node for each clock in the OMAP2 power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/omap2420-clocks.dtsi | 270 +++
arch/arm/boot/dts/omap2420.dtsi| 29 +
arch/arm/boot/dts/omap2430-clocks.dtsi | 344
The clock and clkdev for this are added manually.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 53 ++
drivers/clk/ti/clk-2xxx.c|2 +
include/linux/clk/ti.h |1 +
3 files
On Thu, Feb 13, 2014 at 4:58 PM, Grygorii Strashko
grygorii.stras...@ti.com wrote:
The similar GPIO HW block is used by keystone SoCs as
in Davinci SoCs.
Hence, reuse Davinci GPIO driver for Keystone taking into
account that Keystone contains ARM GIC IRQ controller which
is implemented using
On 03/03/2014 08:52 PM, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [140303 07:11]:
The OMAP_USB2 and OMAP_PIP3 phy devices will not be
detected if the OMAP_OCP2SCP driver is not present.
So select it.
Selecting drivers like this will easily lead into missing
dependencies.
Roger,
On Monday 03 March 2014 08:37 PM, Roger Quadros wrote:
From: Kishon Vijay Abraham I kis...@ti.com
Rename struct omap_control_usb to struct omap_control_phy since it can
be used to control PHY of USB, SATA and PCIE. Also move the driver and
include files under *phy* and made the
On Mon, Mar 03, 2014 at 10:05:22PM -0500, Jason Cooper wrote:
Andrew,
Couple of stupid questions:
- I haven't seen 0/1 nor 1/1 show up anywhere (dt, lakml, inbox), am I
missing something?
Humm, i will check, and do a resend if needed.
On Sun, Mar 02, 2014 at 04:24:15PM +0100,
Hi,
On Monday 03 March 2014 08:37 PM, Roger Quadros wrote:
As this driver is no longer USB specific, use generic clock names.
- Fix PLL_SD_SHIFT from 9 to 10
- As optclk and wkupclk may not be always required, don't bail out
if they aren't available.
I think here too we face the same problem
On 03/04/2014 11:29 AM, Kishon Vijay Abraham I wrote:
Hi,
On Monday 03 March 2014 08:37 PM, Roger Quadros wrote:
As this driver is no longer USB specific, use generic clock names.
- Fix PLL_SD_SHIFT from 9 to 10
- As optclk and wkupclk may not be always required, don't bail out
if they
support pfuze200 chip which remove SW1C and SW4 based on pfuze100.
Signed-off-by: Robin Gong b38...@freescale.com
---
v3:
1. add device tree binding doc for PFUZE200
2. fix building error for non-devicetree case.
---
.../devicetree/bindings/regulator/pfuze100.txt | 96 ++-
On Tue, Mar 04, 2014 at 05:40:36PM +0800, Robin Gong wrote:
support pfuze200 chip which remove SW1C and SW4 based on pfuze100.
Applied, thanks.
signature.asc
Description: Digital signature
On Friday, February 28, 2014 12:22 AM, Lee Jones wrote:
On Thu, 27 Feb 2014, Denis Carikli wrote:
Signed-off-by: Denis Carikli de...@eukrea.com
---
ChangeLog v11-resend-v12:
- Moved the Cc from the commit message to the email patch.
- The documentation is now more clear.
- The
Am Dienstag, den 04.03.2014, 11:06 +0200 schrieb Tomi Valkeinen:
On 27/02/14 19:35, Philipp Zabel wrote:
For simple devices with only one port, it can be made implicit.
The endpoint node can be a direct child of the device node.
snip
@@ -2105,9 +2112,11 @@ struct device_node
On Mon, 3 Mar 2014, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
Some devices have configurable IRQ output polarities. Software might
use IRQ_TYPE_* to determine how to configure such a device's IRQ
output polarity in order to match how the IRQ controller input is
From: Of Vince Bridgers
Hello Florian, thank you for taking the time to comments. My responses inline.
On Sun, Mar 2, 2014 at 6:59 PM, Florian Fainelli f.faine...@gmail.com wrote:
Hello Vince,
It might help reviewing the patches by breaking the patches into:
- the SGDMA bits
- the
Am Freitag, den 28.02.2014, 22:09 +0100 schrieb Sylwester Nawrocki:
[...]
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -1985,6 +1985,37 @@ struct device_node *of_find_next_cache_node(const
struct device_node *np)
}
/**
+ * of_graph_parse_endpoint() - parse common
Am Freitag, den 28.02.2014, 22:09 +0100 schrieb Sylwester Nawrocki:
On 02/27/2014 06:35 PM, Philipp Zabel wrote:
If of_graph_get_next_endpoint is given a parentless node instead of an
endpoint node, it is clearly a bug.
Signed-off-by: Philipp Zabelp.za...@pengutronix.de
---
Hi Sylwester,
Am Freitag, den 28.02.2014, 22:08 +0100 schrieb Sylwester Nawrocki:
Hi Philipp,
Just couple minor comments...
Thanks, I'll fix all of those.
On 02/27/2014 06:35 PM, Philipp Zabel wrote:
The device tree graph bindings as used by V4L2 and documented in
On Tue, 4 Mar 2014, Thomas Gleixner wrote:
On Mon, 3 Mar 2014, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
Some devices have configurable IRQ output polarities. Software might
use IRQ_TYPE_* to determine how to configure such a device's IRQ
output polarity in order
On 03/04/2014 11:20 AM, Linus Walleij wrote:
On Thu, Feb 13, 2014 at 4:58 PM, Grygorii Strashko
grygorii.stras...@ti.com wrote:
The similar GPIO HW block is used by keystone SoCs as
in Davinci SoCs.
Hence, reuse Davinci GPIO driver for Keystone taking into
account that Keystone contains ARM
Hello,
Here is a third version of the patch set that adds a Device Tree
binding and the related code to support fixed PHYs.
Since the second version, the changes have been:
* Rebased on top of v3.14-rc1, and re-tested on hardware.
* Removed the RFC tag, since there seems to be some real
Some Ethernet MACs have a fixed link, and are not connected to a
normal MDIO-managed PHY device. For those situations, a Device Tree
binding allows to describe a fixed link using a special PHY node.
This patch adds:
* A documentation for the fixed PHY Device Tree binding.
* An
Following the introduction of of_phy_register_fixed_link(), this patch
introduces fixed link support in the mvneta driver, for Marvell Armada
370/XP SOCs.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
.../devicetree/bindings/net/marvell-armada-370-neta.txt| 4
Until now, the fixed_phy_add() function was taking as argument
'phy_id', which was used both as the PHY address on the fake fixed
MDIO bus, and as the PHY id, as available in the MII_PHYSID1 and
MII_PHYSID2 registers. However, those two informations are completely
unrelated.
This patch decouples
The existing fixed_phy_add() function has several drawbacks that
prevents it from being used as is for OF-based declaration of fixed
PHYs:
* The address of the PHY on the fake bus needs to be passed, while a
dynamic allocation is desired.
* Since the phy_device instantiation is post-poned
This patch adds dt entry for ahci sata controller and its
corresponding phy controller.phy node has been added w.r.t
new generic phy framework.
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
.../devicetree/bindings/ata/exynos-sata-phy.txt| 14
Add support for pll2650xx in samsung pll file. This pll variant
is close to pll36xx but uses CON2 registers instead of CON1.
Aud_pll in Exynos5260 is pll2650xx and uses this code.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
drivers/clk/samsung/clk-pll.c | 101
Samsung CCF helper functions do not provide support to
register multiple Clock Providers for a given SoC. Due to
this limitation SoC platforms are not able to use these
helpers for registering multiple clock providers and are
forced to bypass this layer.
This layer is modified accordingly to
Add macros which are used as Clock IDs in DT and clock file.
It also adds the documentation for the exynos5260 clocks.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
.../devicetree/bindings/clock/exynos5260-clock.txt | 55 +
include/dt-bindings/clk/exynos5260-clk.h |
From: Pankaj Dubey pankaj.du...@samsung.com
exynos5260 use pll2550xx and it has different bit fields
for P,M,S values as compared to pll2550. Support for
pll2550xx is added here.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
From: Rahul Sharma rahul.sha...@samsung.com
Add clock support for exynos5260 SoC.
This series is based on Kukjin's for-next and
Mike's clk-next branches.
V4:
1) Rework clock file as per Tomasz review comments at
http://www.spinics.net/lists/arm-kernel/msg310116.html.
V3:
1) Removed
Hi Dmitry,
Gentle reminder to comment on this series. Thanks.
cheers,
-roger
On 02/26/2014 05:27 PM, Roger Quadros wrote:
Hi,
This series does the following
- use devres managed resource allocations
- convert to Type-B multi touch protocol
- support upto 5 fingers with hardware
Hi, Tomi and Mark,
On Mon, Feb 17, 2014 at 10:37 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Tue, Jan 14, 2014 at 11:16:24AM +, Zhou Zhu wrote:
add device tree support for mmp fb/controller
the description of DT config is at
Documentation/devicetree/bindings/fb/mmp-disp.txt
Hello all,
On Tue, 4 Mar 2014 11:58:24 +0100, Thomas Petazzoni wrote:
phy_node = of_parse_phandle(dn, phy, 0);
- if (!phy_node) {
- dev_err(pdev-dev, no associated PHY\n);
- err = -ENODEV;
- goto err_free_irq;
+ if
Hi Tomi,
Am Dienstag, den 04.03.2014, 10:58 +0200 schrieb Tomi Valkeinen:
[...]
+int of_graph_parse_endpoint(const struct device_node *node,
+ struct of_endpoint *endpoint)
+{
+ struct device_node *port_node = of_get_parent(node);
Can port_node be NULL? Probably
On 02/28/2014 02:39 PM, Tomi Valkeinen wrote:
On 28/02/14 15:31, Tomi Valkeinen wrote:
Compared to what I've done on OMAP, you don't seem to specify the video
inputs for the tc358764 at all. In this case it's obvious, as the chip
is a child of the DSI master. But the chip could as well be
Hi,
On Saturday, February 22, 2014 04:53:37 PM Hans de Goede wrote:
This avoids the ugliness of creating a nested platform device from probe.
While moving it around anyways, move the mk6q phy init code from probe
to imx_sata_enable, as the phy needs to be re-initialized on resume too,
And one more comment:
On Sun, 2014-02-02 at 02:23 +0400, Vladimir Barinov wrote:
+static int modelgauge_get_property(struct power_supply *psy,
+enum power_supply_property psp,
+union power_supply_propval *val)
+{
+ struct
On 02/28/2014 02:33 PM, Tomi Valkeinen wrote:
I have the same comment here as for the bridge chip: I would specify the
video ports/endpoints between DSI master and the panel, even if you
don't use them at the moment.
Tomi
I have sent my answer in bridge chip subthread.
Regards
Andrzej
--
On 04/03/14 13:36, Philipp Zabel wrote:
Hi Tomi,
Am Dienstag, den 04.03.2014, 10:58 +0200 schrieb Tomi Valkeinen:
[...]
+int of_graph_parse_endpoint(const struct device_node *node,
+ struct of_endpoint *endpoint)
+{
+ struct device_node *port_node =
On 04/03/14 14:00, Andrzej Hajda wrote:
I have made video path binding optional, in case of video bus
if the specific video path is not present driver uses the bus it is
connected to.
In case DSI panel is controlled via different bus the path should be
specified
explicitly.
I have no
On Fri, Feb 28, 2014 at 04:23:27PM +, Russell King - ARM Linux wrote:
On Fri, Feb 28, 2014 at 06:12:23PM +0200, Tomi Valkeinen wrote:
On 28/02/14 17:59, Russell King - ARM Linux wrote:
+dvi0: connector@0 {
+compatible = dvi-connector;
+label = dvi;
+
+
On Fri, Feb 28, 2014 at 04:06:12PM +, Russell King - ARM Linux wrote:
On Fri, Feb 28, 2014 at 02:20:11PM +0200, Tomi Valkeinen wrote:
Add DT binding documentation for HDMI Connector.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
Reviewed-by: Archit Taneja arc...@ti.com
---
This patch adds xilinx CAN controller support.
This driver supports both ZYNQ CANPS and Soft IP
AXI CAN controller.
Signed-off-by: Kedareswara rao Appana appa...@xilinx.com
---
This patch is rebased on the 3.14 rc5 kernel.
Changes for v5:
- Updated the driver with the review comments.
- Remove
On Monday 03 March 2014 10:10 PM, Felipe Balbi wrote:
Hi,
On Mon, Mar 03, 2014 at 05:08:09PM +0530, Kishon Vijay Abraham I wrote:
Added support for optional PHY in dwc3 as not all SoCs having PHYs for DWC3
should be programmed. While this can be considered as a temporary fix,
a long term
On Tuesday 04 March 2014 04:40 PM, Yuvaraj Kumar C D wrote:
This patch adds dt entry for ahci sata controller and its
corresponding phy controller.phy node has been added w.r.t
new generic phy framework.
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
FWIW
Acked-by: Kishon Vijay
On 03/03/2014 08:34 AM, Mark Brown wrote:
On Wed, Feb 26, 2014 at 11:14:25AM +0200, Jyri Sarha wrote:
This commit adds a bare bones driver support for TLV320AIC31XX family
audio codecs. The driver adds basic stereo playback trough headphone
and speaker outputs and mono capture trough microphone
Hi Tomi,
Am Freitag, den 28.02.2014, 09:36 +0200 schrieb Tomi Valkeinen:
On 27/02/14 18:54, Philipp Zabel wrote:
- One IPU enabled, one disabled: nothing special here, just set the
other IPU to status=disabled in the DT data. The driver for the
enabled IPU would register the required DRM
Since the RFC version of the patches [1] I have addressed Mark Browns
comments [2] as described in my mail here [3].
Besr regards,
Jyri
[1]
http://mailman.alsa-project.org/pipermail/alsa-devel/2014-February/073289.html
[2]
The tlv320aic32x4 related files were wrongly placed after tlv320aic3x files.
Signed-off-by: Jyri Sarha jsa...@ti.com
---
sound/soc/codecs/Makefile |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index
This commit adds a bare bones driver support for TLV320AIC31XX family
audio codecs. The driver adds basic stereo playback trough headphone
and speaker outputs and mono capture trough microphone inputs.
The driver is currently missing support at least for mini DSP features
and jack detection. I
Add machine driver support for AM43xx-ePOS-EVM and update associated
device tree binding document.
Signed-off-by: Jyri Sarha jsa...@ti.com
---
.../bindings/sound/davinci-evm-audio.txt |9 +++--
sound/soc/davinci/davinci-evm.c| 41
2 files
Add support for am335x and am43x based boards with tlv320aic31xx
compatible codec connected to McASP.
Signed-off-by: Jyri Sarha jsa...@ti.com
---
sound/soc/davinci/Kconfig | 12
sound/soc/davinci/Makefile |1 +
2 files changed, 13 insertions(+)
diff --git
+static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = {
+ SND_SOC_DAPM_HP(Headphone Jack, NULL),
+ SND_SOC_DAPM_SPK(Speaker, NULL),
+ SND_SOC_DAPM_MIC(Mic Jack, NULL),
+};
+
+/* Logic for EVMs with an aic31xx */
+static int evm_aic31xx_init(struct
Am Freitag, den 28.02.2014, 21:03 +0100 schrieb Arnd Bergmann:
On Friday 28 February 2014, Lucas Stach wrote:
+Required properties:
+- compatible: fsl,imx6q-pcie
+- reg: base addresse and length of the pcie controller
+- interrupts: First entry must contain interrupt handle for controller
On Tuesday 04 March 2014, Lucas Stach wrote:
Right, we should be able to reuse the clock names. Though I'm not really
sure how the Samsung clocks maps to those used on i.MX, as the names are
a bit generic. Maybe someone from Samsung could shed a bit of light on
this.
On i.MX6 the clock
On Fri, Feb 28, 2014 at 9:28 AM, Lucas Stach l.st...@pengutronix.de wrote:
This is the recommended method of doing the IRQ
mapping. For old devicetrees we fall back to the
previous practice.
Signed-off-by: Lucas Stach l.st...@pengutronix.de
---
drivers/pci/host/pcie-designware.c | 8
On Mon, Mar 03, 2014 at 02:04:17PM +, Rob Herring wrote:
Adding Will...
Thanks Rob!
On Fri, Feb 28, 2014 at 9:24 AM, Arnd Bergmann a...@arndb.de wrote:
On Friday 28 February 2014 09:14:19 Rob Herring wrote:
I know Will D was not a fan of this property. Primarily I believe
because
Hi,
This is the seventh version of this patchset. First and most significant change
is that this patchset includes only patches touching the Generic PHY Framework.
Patches to the USB controllers were stripped as they require additional work.
S5PV210 support is also omitted - it requires more
Previously the of_phy_get function took a struct device * and
was declared static. It was impossible to call it from
another driver and thus it was impossible to get phy defined
for a given node. The old function was renamed to _of_phy_get
and was left for internal use. of_phy_get function was
Add a new driver for the Exynos USB 2.0 PHY. The new driver uses the generic
PHY framework. The driver includes support for the Exynos 4210 and 4x12
SoC families.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
.../devicetree/bindings/phy/samsung-phy.txt| 53
Adding devm_of_phy_get will allow to get phys by supplying a
pointer to the struct device_node instead of struct device.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
drivers/phy/phy-core.c | 31 +++
include/linux/phy/phy.h |8
2 files changed,
Add support for Exynos 5250. This driver is to replace the old
USB 2.0 PHY driver.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
.../devicetree/bindings/phy/samsung-phy.txt|1 +
drivers/phy/Kconfig| 11 +
drivers/phy/Makefile
Am Dienstag, den 04.03.2014, 15:53 +0100 schrieb Arnd Bergmann:
On Tuesday 04 March 2014, Lucas Stach wrote:
Right, we should be able to reuse the clock names. Though I'm not really
sure how the Samsung clocks maps to those used on i.MX, as the names are
a bit generic. Maybe someone from
On 03/04/2014 04:12 PM, Lars-Peter Clausen wrote:
+static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = {
+SND_SOC_DAPM_HP(Headphone Jack, NULL),
+SND_SOC_DAPM_SPK(Speaker, NULL),
+SND_SOC_DAPM_MIC(Mic Jack, NULL),
+};
+
+/* Logic for EVMs with an aic31xx */
+static int
Am Dienstag, den 04.03.2014, 14:21 +0200 schrieb Tomi Valkeinen:
On 04/03/14 13:36, Philipp Zabel wrote:
[...]
Can port_node be NULL? Probably only if something is quite wrong, but
maybe it's safer to return error in that case.
both of_property_read_u32 and of_node_put can handle
Make it easier to discover the domain number of a bus by storing
the number in pci_host_bridge for the root bus. Several architectures
have their own way of storing this information, so it makes sense
to try to unify the code. While at this, add a new function that
creates a root bus in a given
From: Catalin Marinas catalin.mari...@arm.com
The patch moves the PCI I/O space (currently at 64K) before the
earlyprintk mapping and extends it to 16MB.
Signed-off-by: Catalin Marinas catalin.mari...@arm.com
diff --git a/Documentation/arm64/memory.txt b/Documentation/arm64/memory.txt
index
Hi,
This patch adds support for PCI to AArch64. It is based on my v5 patch
that adds support for creating generic host bridge structure from
device tree. With that in place, I was able to boot a platform that
has PCIe host bridge support and use a PCIe network card.
Changes from v4:
- Fixed
Use the generic host bridge functions to provide support for
PCI Express on arm64. There is no support for ISA memory.
Signed-off-by: Liviu Dudau liviu.du...@arm.com
create mode 100644 arch/arm64/include/asm/pci.h
create mode 100644 arch/arm64/kernel/pci.c
diff --git a/arch/arm64/Kconfig
The inline version of ioport_map() that gets used when !CONFIG_GENERIC_IOMAP
is wrong. It returns a mapped (i.e. virtual) address that can start from
zero and completely ignores the PCI_IOBASE and IO_SPACE_LIMIT that most
architectures that use !CONFIG_GENERIC_MAP define.
Signed-off-by: Liviu
This is a useful function and we should make it visible outside the
generic PCI code. Export it as a GPL symbol.
Signed-off-by: Liviu Dudau liviu.du...@arm.com
diff --git a/drivers/pci/host-bridge.c b/drivers/pci/host-bridge.c
index 06ace62..8708b652 100644
--- a/drivers/pci/host-bridge.c
+++
This is v5 of my attempt to add support for a generic pci_host_bridge
controller created
from a description passed in the device tree.
Changes from v4:
- Export pci_find_host_bridge() to be used by arch code. There is scope for
making the arch/arm64 version of pci_domain_nr the default
The ranges property for a host bridge controller in DT describes
the mapping between the PCI bus address and the CPU physical address.
The resources framework however expects that the IO resources start
at a pseudo port address 0 (zero) and have a maximum size of IO_SPACE_LIMIT.
The conversion
Before commit 7b5436635800 the pci_host_bridge was created before the root bus.
As that commit has added a needless dependency on the bus for
pci_alloc_host_bridge()
the creation order has been changed for no good reason. Revert the order of
creation as we are going to depend on the
Some architectures do not share x86 simple view of the I/O space and
instead use a range of addresses that map to external devices. For PCI,
these ranges can be expressed by OF bindings in a device tree file.
Introduce a pci_register_io_range() helper function that can be used
by the architecture
pci_alloc_child_bus() uses the newly allocated child bus to figure
out the domain number that is going to use for setting the device
name. A better option is to use the parent bus domain number.
Signed-off-by: Liviu Dudau liviu.du...@arm.com
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
Several platforms use a rather generic version of parsing
the device tree to find the host bridge ranges. Move the common code
into the generic PCI code and use it to create a pci_host_bridge
structure that can be used by arch code.
Based on early attempts by Andrew Murray to unify the code.
Used
On 03/04/2014 03:04 AM, Thomas Gleixner wrote:
On Mon, 3 Mar 2014, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
Some devices have configurable IRQ output polarities. Software might
use IRQ_TYPE_* to determine how to configure such a device's IRQ
output polarity in order to
On Fri, Feb 28, 2014 at 03:00:00PM -0800, Tony Lindgren wrote:
* Suman Anna s-a...@ti.com [140228 12:46]:
Hi Joerg, Tony,
This is an updated series of the OMAP IOMMU DT adaptation intended
for 3.15 merge window, addressing the comments from the v2 series.
This series is rebased onto
Add the DT nodes to enable the watchdog support available on
Armada 380/385 SoC.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
arch/arm/boot/dts/armada-38x.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/armada-38x.dtsi
Add the DT nodes to enable the watchdog support available on
Armada 375 SoC.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
arch/arm/boot/dts/armada-375.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/armada-375.dtsi
In order to support other SoCs, it's needed to have a different enabled()
implementation for each SoC. This commit adds no functionality, and it
consists of preparation work.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
drivers/watchdog/orion_wdt.c | 15 +--
This commit adds support for the Armada 375 and Armada 380 SoCs.
This SoC variant has a second RSTOUT register, in addition to the already
existent, which is shared with the system-controller. To handle this RSTOUT,
we introduce a new MMIO register 'rstout_mask' to be required on
Here's a new patchset adding support for watchdog on Armada 375 and
Armada 38x SoCs. Regarding the previous patchset, this time we're handling
the SoCs differences in the watchdog driver itself.
The new Armada 375/385 SoCs have two registers for the watchdog RSTOUT:
1. It has a dedicated
This commit separates the RSTOUT register mapping for the different
compatible strings supported by the driver. This is needed as
preparation work to support other SoCs.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
drivers/watchdog/orion_wdt.c | 28
In order to support other SoCs, it's needed to have a different stop()
implementation for each SoC. This commit adds no functionality, and it
consists of preparation work.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
drivers/watchdog/orion_wdt.c | 26
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