Documenting the microchip,active-high property for interrupt pin
behavior.
Signed-off-by: Matt Ranostay
---
Documentation/devicetree/bindings/input/cap1106.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/input/cap1106.txt
b/Documentation/devicetree/
Some applications need to use the active-high push-pull interrupt
option. This allows it be enabled in the device tree child node.
Signed-off-by: Matt Ranostay
---
drivers/input/keyboard/cap1106.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/input/keyboard/cap1106.c b/driver
Several other variants of the cap11xx device exists with a varying
number of capacitance detection channels. Add support for creating
the channels dynamically.
Signed-off-by: Matt Ranostay
---
drivers/input/keyboard/cap1106.c | 54 +++-
1 file changed, 26 inse
These patches enable using cap11xx devices that have different
number of capacitance channels, and using active-high on the
interrupt output.
Matt Ranostay (3):
cap1106: Add support for various cap11xx devices
cap1106: support for active-high interrupt option
dt: cap1106 active-high property
On Tuesday, September 16, 2014 02:52:31 PM Mika Westerberg wrote:
> This is a second revision of the patches first submitted here [1].
>
> The recent publication of the ACPI 5.1 specification [2] adds a reserved name
> for Device Specific Data (_DSD, Section 6.2.5). This mechanism allows for
> pas
On 09/20/2014 08:06 PM, Sebastian Hesselbarth wrote:
> Currently, Armada XP PCIe nodes are numbered pcie@,0 with N just
> incrementing. To reflect port/lane relationship, rename the nodes
> to pcie@,. While at it, add node aliases to each of pcie
> controller and port nodes and get rid of now redun
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On Saturday, September 20, 2014 02:23:19 PM Wolfram Sang wrote:
>
> --bAmEntskrkuBymla
> Content-Type: text/plain; charset=us-ascii
> Content-Disposition: inline
> Content-Transfer-Encoding: quoted-printable
>
> On Fri, Sep 19, 2014 at 08:27:39PM +0200, Ulf Hansson wrote:
> > Previously only the
Ben Gamari writes:
> Hi Boris,
>
> I'm just returning to this now.
>
>
> Greg Kroah-Hartman writes:
>
>> I don't understand what makes GPIO's "special" enough to get included in
>> the driver core like this, and called for each and every device that is
>> added to the system.
>>
> I'm also a bit
Hi Boris,
I'm just returning to this now.
Greg Kroah-Hartman writes:
> I don't understand what makes GPIO's "special" enough to get included in
> the driver core like this, and called for each and every device that is
> added to the system.
>
I'm also a bit confused why GPIOs ended up in the d
Currently, Armada XP PCIe nodes are numbered pcie@,0 with N just
incrementing. To reflect port/lane relationship, rename the nodes
to pcie@,. While at it, add node aliases to each of pcie
controller and port nodes and get rid of now redundant port/lane
comments.
Signed-off-by: Sebastian Hesselbart
Armada XP pcie controller and port nodes gained aliases, make use of them.
Signed-off-by: Sebastian Hesselbarth
---
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: Bjorn Helgaas
Cc: Jason Cooper
Cc: Andrew Lunn
Cc: Gregory Clement
Cc: Thomas Peta
The PCIe controller on Port 0 of Lenovo ix4-300d is configured as
quad-lane x4. Correct the marvell,pcie-lane property accordingly.
Signed-off-by: Sebastian Hesselbarth
---
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: Bjorn Helgaas
Cc: Jason Coope
Some PCIe controllers found on Armada XP SoCs can be configured as
either four single-lane x1 or one quad-lane x4 PCIe. Although we are
not (yet) interested in the physical configuration of the PCIe
controller, we will need it when proper PHY support for PCIe is added.
Adapt the driver to the amend
Some PCIe controllers found on Armada XP SoCs can be configured as
either four single-lane x1 or one quad-lane x4 PCIe. The current
binding documentation is a bit unclear about it, so amend the
property description of "marvell,pcie-lane" to allow multiple lanes
to be passed. Also, rework the bindin
On 09/17/2014 08:30 PM, Liviu Dudau wrote:
> Add of_pci_get_domain_nr() to retrieve the PCI domain number
> of a given device from DT. If the information is not present,
> the function can be requested to allocate a new domain number.
>
> Cc: Bjorn Helgaas
> Cc: Arnd Bergmann
> Cc: Grant Likely
On 09/17/2014 08:30 PM, Liviu Dudau wrote:
> The ranges property for a host bridge controller in DT describes
> the mapping between the PCI bus address and the CPU physical address.
> The resources framework however expects that the IO resources start
> at a pseudo "port" address 0 (zero) and have
From: Suravee Suthikulpanit
This patch implelments the ARM64 version of arch_setup_msi_irqs(),
which does not return 1 for when PCI_CAP_ID_MSI and nvec > 1.
Signed-off-by: Suravee Suthikulpanit
Acked-by: Marc Zyngier
Cc: Mark Rutland
Cc: Jason Cooper
Cc: Catalin Marinas
Cc: Will Deacon
---
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in ARM
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the following patch set which
implements PCI supports for ARM64:
[PATCH v11 00/10] Support for creati
Mike Turquette writes:
> Quoting Arnd Bergmann (2014-08-24 05:08:19)
>> On Sunday 24 August 2014, Robert Jarzmik wrote:
>> > > By default, I'd expect Haojian to pick up the patches and send
>> > > us a pull request. He sent an Ack, but also didn't make it clear
>> > > that we should pick them up.
On Saturday 20 September 2014 09:13 PM, Hauke Mehrtens wrote:
On 09/20/2014 05:40 PM, Varka Bhadram wrote:
On Saturday 20 September 2014 06:32 PM, Hauke Mehrtens wrote:
This driver is used by the bcm53xx ARM SoC code. Now it is possible to
give the address of the chipcommon core in device tree
On 09/20/2014 05:40 PM, Varka Bhadram wrote:
> On Saturday 20 September 2014 06:32 PM, Hauke Mehrtens wrote:
>> This driver is used by the bcm53xx ARM SoC code. Now it is possible to
>> give the address of the chipcommon core in device tree and bcma will
>> search for all the other cores.
>
> (...
On Saturday 20 September 2014 06:32 PM, Hauke Mehrtens wrote:
This driver is used by the bcm53xx ARM SoC code. Now it is possible to
give the address of the chipcommon core in device tree and bcma will
search for all the other cores.
(...)
+
+static const struct of_device_id bcma_host_soc_of_
[adding Kukjin as cc]
Hello Ajay,
On Sat, Sep 20, 2014 at 1:22 PM, Ajay kumar wrote:
>> Generally speaking, I sense that we have different views of how display
>> devices and drivers are structured. You say "If some XYZ platform wishes
>> to pick the DT node via a different method, they are alwa
* Thomas Gleixner [140919 19:08]:
> On Fri, 19 Sep 2014, Tony Lindgren wrote:
> > * Thomas Gleixner [140919 12:47]:
> > > Why on earth are you wanting tasklets in there? That's just silly,
> > > really.
> >
> > Lack of a framework on driver side to cope with this in a generic
> > way? :p
>
> So
The Ethernet controller available in Meson6 and Meson8 SoCs is a
Synopsys DesignWare MAC IP core, already supported by the stmmac
driver.
This glue layer implements some platform-specific settings needed by
the Amlogic variant.
Signed-off-by: Beniamino Galvani
---
drivers/net/ethernet/stmicro/s
Add the device tree bindings documentation for the Amlogic Meson
variant of the Synopsys DesignWare MAC.
Signed-off-by: Beniamino Galvani
---
.../devicetree/bindings/net/meson-dwmac.txt| 25 ++
1 file changed, 25 insertions(+)
create mode 100644 Documentation/devicet
Hi,
the Ethernet controller available in Amlogic Meson6 and Meson8 SoCs is
a Synopsys DesignWare MAC IP core, already supported by the stmmac
driver.
These patches add a glue layer to the driver for the platform-specific
settings required by the Amlogic variant.
This has been tested on a Amlogic
On 20 September 2014 15:02, Hauke Mehrtens wrote:
> This driver is used by the bcm53xx ARM SoC code. Now it is possible to
> give the address of the chipcommon core in device tree and bcma will
> search for all the other cores.
Looks fine, thanks!
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This driver is used by the bcm53xx ARM SoC code. Now it is possible to
give the address of the chipcommon core in device tree and bcma will
search for all the other cores.
Signed-off-by: Hauke Mehrtens
---
Documentation/devicetree/bindings/bus/bcma.txt | 39
drivers/bcma/bcma_privat
It is not possible to auto detect the irq numbers used by the cores on
an arm SoC. If bcma was registered with device tree it will search for
some device tree nodes with the irq number and add it to the core
configuration.
Signed-off-by: Hauke Mehrtens
---
drivers/bcma/main.c | 49 ++
On Fri, Sep 19, 2014 at 08:27:39PM +0200, Ulf Hansson wrote:
> Previously only the ACPI PM domain was supported by the i2c bus.
>
> Let's convert to the common attach/detach functions for PM domains,
> which currently means we are extending the support to include the
> generic PM domain as well.
>
Hi Abhilash,
On Sat, Sep 13, 2014 at 2:20 PM, Abhilash Kesavan wrote:
> The following patches are tested based on Kgene's for-next tree.
> https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next
>
> Following patches are required for this series:
> 1- "tty/serial: fix
Hi,
thanks for the submission.
On Mon, Aug 25, 2014 at 01:51:22PM +0200, Anders Berg wrote:
> Add I2C bus driver for the controller found in the LSI Axxia family SoCs. The
> driver implements 10-bit addressing and SMBus transfer modes via emulation
> (including SMBus block data read).
>
> Signed
Hi Abhilash,
On Sat, Sep 13, 2014 at 2:20 PM, Abhilash Kesavan wrote:
> From: Naveen Krishna Chatradhi
>
> Add intial pin configuration nodes for EXYNOS7.
>
> Signed-off-by: Naveen Krishna Chatradhi
> Signed-off-by: Abhilash Kesavan
> Cc: Rob Herring
> Cc: Catalin Marinas
> Cc: Tomasz Figa
On Fri, Sep 19, 2014 at 7:58 PM, Tomi Valkeinen wrote:
> On 19/09/14 16:59, Ajay kumar wrote:
>
>> I am not really able to understand, what's stopping us from using this
>> bridge on a board with "complex" display connections. To use ps8622 driver,
>> one needs to "attach" it to the DRM framework.
Hi Brian,
On Fri, 19 Sep 2014 21:34:38 -0700
Brian Norris wrote:
> Hi Boris,
>
> On Mon, Aug 18, 2014 at 07:26:26PM +0200, Boris BREZILLON wrote:
> > This patch series adds support for the sunxi NAND Flash Controller (NFC)
> > block.
> >
> > These two patches only add support for the basic NAN
On Thu, Sep 18, 2014 at 11:24:40AM +0800, Chen-Yu Tsai wrote:
> Add the DMA controller node and DMA bindings to the supported devices.
>
> Signed-off-by: Chen-Yu Tsai
Applied, thanks!
Maxime
--
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Embedded Linux, Kernel and Android engineering
http://free-electrons.
On Thu, Sep 18, 2014 at 11:24:39AM +0800, Chen-Yu Tsai wrote:
> The A23 SoC has the same dma engine as the A31 (sun6i), with a
> reduced amount of endpoints and physical channels. Add the proper
> config data and compatible string to support it.
>
> A slight difference in sun8i is an undocumented
On Wed, Sep 17, 2014 at 12:01:46AM +0800, Chen-Yu Tsai wrote:
> On Tue, Sep 16, 2014 at 11:48 PM, Maxime Ripard
> wrote:
> > On Fri, Sep 12, 2014 at 10:10:25AM +0800, Chen-Yu Tsai wrote:
> >> On Fri, Sep 12, 2014 at 5:15 AM, Maxime Ripard
> >> wrote:
> >> > On Sat, Sep 06, 2014 at 06:47:27PM +080
On 09/19/2014 10:14 PM, Sebastian Hesselbarth wrote:
> There is an I2C eeprom connected on Lenovo ix4-300d, add the
> corresponding node.
>
> Signed-off-by: Sebastian Hesselbarth
> ---
...
> ---
> arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts | 5 +
> 1 file changed, 5 insertions(+)
>
> d
On Wed, Aug 20, 2014 at 04:29:08PM +0200, Romain Baeriswyl wrote:
> From: Romain Baeriswyl
>
> Some legacy devices support ony I2C standard mode at 100kHz.
> This patch allows to select the standard mode through the DTS
> with the use of the existing clock-frequency parameter.
>
> When clock-fre
This patch adds the devicetree documentation for the
Cirrus Logic CLPS711X SPI driver.
Signed-off-by: Alexander Shiyan
---
.../devicetree/bindings/spi/spi-clps711x.txt | 20
1 file changed, 20 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/sp
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