Hi Grygorii,
On 9/29/14 7:38 AM, Grygorii Strashko wrote:
This patch switches Keystone 2 PM code to use Generic PM domains
instead of PM clock domains because of the lack of DT support
for the last.
Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
IMO, this approach is much better.
On 10/2/14 12:17 PM, Santosh Shilimkar wrote:
On Monday 29 September 2014 10:38 AM, Grygorii Strashko wrote:
This patch switches Keystone 2 PM code to use Generic PM domains
instead of PM clock domains because of the lack of DT support
for the last.
Signed-off-by: Grygorii Strashko
Robert Nelson skrev:
The TPS65217C used on the boneblack defaults to 1.5v on startup for dcdc1_reg.
While 1.35v ddr3 memory is actually used. This was discovered by a user during
a schematic review of his beaglebone-black clone, a u-boot patch will also also
be submitted.
Isn't it dual voltage,
Hi!
From: Dinh Nguyen dingu...@opensource.altera.com
There are certain drivers that are required to get loaded very early using
arch_initcall. An example of such a driver is the SOCFPGA's FPGA bridge
driver.
This driver has to get loaded early because it needs to enable FPGA components
Signed-off-by: Carlo Caione ca...@caione.org
---
.../bindings/reset/amlogic,meson6-rst-mgr-ao.txt | 14 ++
1 file changed, 14 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reset/amlogic,meson6-rst-mgr-ao.txt
diff --git
This patch adds support for the reset controller found on the Amlogic
MesonX SoCs. For several devices in the AO (Always-On) power domain, it
is possible to reset them by programming a specific bit in a register.
Signed-off-by: Carlo Caione ca...@caione.org
---
drivers/reset/Makefile | 1
Add the node for the reset controller in the DTSI.
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/boot/dts/meson.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index e6539ea..1ca864e 100644
---
Apparently several IPs found in the MesonX SoCs can be reset by programming a
specific bit in a register in the so called AO (Always-On) domain. From the
documentation released by Amlogic under NDA it is not clear which devices can
be reset acting on this register. So far from the sources release
On Sun, Oct 12, 2014 at 04:54:37PM +0200, Carlo Caione wrote:
This patch adds support for the reset controller found on the Amlogic
MesonX SoCs. For several devices in the AO (Always-On) power domain, it
is possible to reset them by programming a specific bit in a register.
Hi Carlo,
[...]
On Sun, Oct 12, 2014 at 6:03 PM, Beniamino Galvani b.galv...@gmail.com wrote:
Hi Carlo,
Hi Beniamino,
[...]
+
+static int meson_reset_probe(struct platform_device *pdev)
+{
+ struct meson_reset_data *data;
+ struct resource *res;
+
+ /*
+ * The binding was mainlined
Get DTB pointer (located in r2) from SRC_GPR3 (argument register
for secondary core)
Signed-off-by: Stefan Agner ste...@agner.ch
---
This is clearly a hack but it works around the need of a boot loader
on the Cortex-M4. I guess there is no way neither its acceptable to
do this on machine level..?
So far only vectors for up to 48 external interrupts have been
registred in the vector table. Increase the amount of registred
external vectors to 112. Also add a warning in case NVIC reports
support for more interrupts than 128.
Signed-off-by: Stefan Agner ste...@agner.ch
---
Add support for !MMU low level debug required for the secondary
Cortex-M4 core in Vybrid.
Signed-off-by: Stefan Agner ste...@agner.ch
---
arch/arm/include/debug/vf.S | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/include/debug/vf.S b/arch/arm/include/debug/vf.S
index
Add defconfig for Linux on Vybrid (vf610) on the secondary Cortex-
M4 CPU. Currently, we use a XIP image which is loaded to the end
of RAM at 0x8f00. DRAM base address is at 0x8800.
Signed-off-by: Stefan Agner ste...@agner.ch
---
arch/arm/configs/vf610m4_defconfig | 37
This adds Vybrid SoC support for the !MMU Cortex-M4 core. The patchset is
its current state is more a collection of hacks than anything mergabel,
advice and ideas how to beat it in good shape are welcome. I added some
thoughts as comments in the individual patches.
I wrote also some more info
Add the minimal dependencies required to use the Vybrid PIT
clocksource driver. Those are not part of the SoC dependencies.
Signed-off-by: Stefan Agner ste...@agner.ch
---
drivers/clocksource/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clocksource/Kconfig
This adds an initial device tree to run Linux on the Cortex-M4 on
Vybrid.
HACK: Because we include armv7-m.dtsi, the soc node happens to
be before the clock node. This is a problem for vf610-clk.c, which
tries to optain the fixed clocks defined in the clock nodes. But
because clock drivers are
This patch adds a new machine ARCH_MXCM4 which requires !MMU and
!MULTIARCH and is meant as machine for the hetregenous multi-core
Vybrid/i.MX SoC's to run Linux on the Cortex-M4.
The first SoC supported is Vybrid on Cortex-M4 (SOC_VF610M4).
Signed-off-by: Stefan Agner ste...@agner.ch
---
Not
Hello,
On Sun, Oct 12, 2014 at 08:13:56PM +0200, Stefan Agner wrote:
Add the minimal dependencies required to use the Vybrid PIT
clocksource driver. Those are not part of the SoC dependencies.
Signed-off-by: Stefan Agner ste...@agner.ch
---
drivers/clocksource/Kconfig | 2 ++
1 file
Some systems may require a different resistor than the default one (4K).
This adds a property in sgtl5000 codec.
It keeps the default of 4K when nothing is specified so it does not break
existing code.
Signed-off-by: Jean-Michel Hautbois jean-michel.hautb...@vodalys.com
---
On Sat, Oct 11, 2014 at 07:50:07PM -0500, Felipe Balbi wrote:
Hi,
On Sat, Oct 11, 2014 at 12:20:04PM +0200, Johan Hovold wrote:
On Fri, Oct 10, 2014 at 01:02:56PM -0500, Felipe Balbi wrote:
On Fri, Oct 10, 2014 at 01:00:54PM -0500, Felipe Balbi wrote:
On Thu, Oct 09, 2014 at
On Sunday 12 October 2014 20:13:55 Stefan Agner wrote:
Add support for !MMU low level debug required for the secondary
Cortex-M4 core in Vybrid.
Signed-off-by: Stefan Agner ste...@agner.ch
---
arch/arm/include/debug/vf.S | 10 ++
1 file changed, 10 insertions(+)
diff --git
On Sunday 12 October 2014 20:13:57 Stefan Agner wrote:
This patch adds a new machine ARCH_MXCM4 which requires !MMU and
!MULTIARCH and is meant as machine for the hetregenous multi-core
Vybrid/i.MX SoC's to run Linux on the Cortex-M4.
The first SoC supported is Vybrid on Cortex-M4
On Sunday 12 October 2014 20:13:58 Stefan Agner wrote:
This adds an initial device tree to run Linux on the Cortex-M4 on
Vybrid.
HACK: Because we include armv7-m.dtsi, the soc node happens to
be before the clock node. This is a problem for vf610-clk.c, which
tries to optain the fixed clocks
On Sunday 12 October 2014 20:14:00 Stefan Agner wrote:
Get DTB pointer (located in r2) from SRC_GPR3 (argument register
for secondary core)
Signed-off-by: Stefan Agner ste...@agner.ch
---
This is clearly a hack but it works around the need of a boot loader
on the Cortex-M4. I guess there
Fix the compatible for the UART to make it consistent with the other
compatibles for Meson6 and Meson8 and to avoid problems when the
meson8b will be introduced with a different UART driver.
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/boot/dts/meson.dtsi| 8
Hi,
this is a driver for the IR receiver available in Amlogic Meson6 and
Meson8 SoCs. The device can operate in two modes: in NEC mode the
hardware can decode frames using the NEC IR protocol, while in
general mode the receiver simply reports the duration of pulses and
spaces for software
Amlogic Meson SoCs include a infrared remote control receiver that can
operate in two modes: in NEC mode the hardware can decode frames
using the NEC IR protocol, while in general mode the receiver simply
reports the duration of pulses and spaces for software decoding.
This is a driver for the IR
Signed-off-by: Beniamino Galvani b.galv...@gmail.com
---
arch/arm/boot/dts/meson.dtsi | 7 +++
arch/arm/boot/dts/meson8-vega-s89e.dts | 6 ++
arch/arm/boot/dts/meson8.dtsi | 7 +++
3 files changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/meson.dtsi
This adds binding documentation for the infrared remote control
receiver available in Amlogic Meson SoCs.
Signed-off-by: Beniamino Galvani b.galv...@gmail.com
---
Documentation/devicetree/bindings/media/meson-ir.txt | 14 ++
1 file changed, 14 insertions(+)
create mode 100644
On Sun, Oct 12, 2014 at 3:39 PM, Jean-Michel Hautbois
jean-michel.hautb...@vodalys.com wrote:
+ if (np) {
+ if (!of_property_read_u32(np,
+ sgtl5000-micbias-resistor, value)) {
+ switch (value) {
+ case 1:
Some systems may require a different resistor than the default one (4K).
This adds a property in sgtl5000 codec.
It keeps the default of 4K when nothing is specified so it does not break
existing code.
v2: modify the default case on DT parsing
Signed-off-by: Jean-Michel Hautbois
Hi Fabio,
2014-10-12 23:15 GMT+02:00 Fabio Estevam feste...@gmail.com:
On Sun, Oct 12, 2014 at 3:39 PM, Jean-Michel Hautbois
jean-michel.hautb...@vodalys.com wrote:
+ if (np) {
+ if (!of_property_read_u32(np,
+ sgtl5000-micbias-resistor, value)) {
Stanimir Varbanov schrieb am 24.09.2014 14:56:
The voltage ADC is peripheral of Qualcomm SPMI PMIC chips. It has
15bits resolution and register space inside PMIC accessible across
SPMI bus.
The vadc driver registers itself through IIO interface.
Quite a lot of changes. Please see my comments
Stanimir Varbanov schrieb am 25.09.2014 17:30:
Hi Ivan,
On 09/25/2014 03:47 PM, Ivan T. Ivanov wrote:
Hi Stan, few comment bellow.
On Wed, 2014-09-24 at 15:56 +0300, Stanimir Varbanov wrote:
The voltage ADC is peripheral of Qualcomm SPMI PMIC chips. It has
15bits resolution and register
Hi Jean-Michel,
On Sun, Oct 12, 2014 at 6:42 PM, Jean-Michel Hautbois
jean-michel.hautb...@vodalys.com wrote:
You are right of course, second version sent. I have a patch wich adds
MicBias voltage support too, but it will be on top of this one, is
this a problem ?
In this case you could send
On 10/02/2014 08:27 AM, Dmitry Torokhov wrote:
Hi Ulf,
On Fri, Sep 19, 2014 at 08:27:40PM +0200, Ulf Hansson wrote:
Previously only the ACPI PM domain was supported by the sdio bus.
Let's convert to the common attach/detach functions for PM domains,
which currently means we are extending
Hi Vivek,
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
As we discussed before, Exynos7 SoCs have 7 clocks to be controlled
by the driver. Adding only sclk is not enough.
Signed-off-by: Vivek Gautam
Hi Vivek,
Exynos7 SoC has now separate gate control for 125MHz pipe3 phy
clock, as well as 60MHz utmi phy clock.
So get the same and control in the phy-exynos5-usbdrd driver.
In case of the PHY the situation is pretty much the same as with
DWC3 core. Here we should control 6 clocks to make
Hi Vivek,
Some Exynos SoCs have a separate regulator controlling a
I guess you meant the Exynos based *boards* instead of SoCs,
since Exynos SoCs don't have any boost regulators.
Boost 5V supply which goes as input for VBUS regulator.
So adding a control for the same in driver, to enable
On Mon, Oct 13, 2014 at 10:36 AM, Anton Tikhomirov
av.tikhomi...@samsung.com wrote:
Hi Vivek,
Some Exynos SoCs have a separate regulator controlling a
I guess you meant the Exynos based *boards* instead of SoCs,
since Exynos SoCs don't have any boost regulators.
Right, should be boards
2014-10-13 0:39 GMT+02:00 Fabio Estevam feste...@gmail.com:
Hi Jean-Michel,
On Sun, Oct 12, 2014 at 6:42 PM, Jean-Michel Hautbois
jean-michel.hautb...@vodalys.com wrote:
You are right of course, second version sent. I have a patch wich adds
MicBias voltage support too, but it will be on top
This patch set includes regulator and backlight driver for SKY81452.
Also it includes documents for device tree and module.
The initial version of sky81452-regulator was applied. Fo this, incremental
patches are included.
v4:
Removed MODULE_VERSION()
Modified license to GPLv2
Removed calling to
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
---
Changes v4:
Removed MODULE_VERSION()
Modified license to GPLv2
Changes v3:
Fixed the backlight name from 'sky81452-bl' to 'sky81452-backlight'
Assigned mfd_cell.of_compatible for binding device node
Modified error messages
Changes v2:
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
---
Changes v4:
Nothing
Changes v3:
Nothing
Changes v2:
Added reg attribute for I2C slave address
Documentation/devicetree/bindings/mfd/sky81452.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
---
Changes v4:
Reordering header files for readability
Removed calling to backlight_device_unregister()
- because devm_backlight_device_register() was used
Removed MODULE_VERSION()
Modified license to GPLv2
Changes v3:
Modified DBG messages
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
---
Changes v4:
Nothing
Changes v3:
Nothing
Changes v2:
Add SKY81452 to the Trivial Devices list
Documentation/devicetree/bindings/i2c/trivial-devices.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
---
Changes v4:
Nothing
Changes v3:
Nothing
Changes v2:
Added 'compatible' attribute in the driver
Documentation/devicetree/bindings/regulator/sky81452-regulator.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
---
Changes v4:
Nothing
Changes v3:
Nothing
Changes v2:
Added reg attribute for I2C slave address
.../video/backlight/sky81452-backlight.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
---
Changes v4:
Removed MODULE_VERSION()
Modified license to GPLv2
Changes v3:
Modified to return ENODATA when of_node is NULL
Modified the messages in error cases
Changes v2:
Added 'compatible' attribute in the driver
Added message for
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
---
Changes v4:
Nothing
Changes v3:
Nothing
Changes v2:
Added vendor prefix for Skyworks Solutions, Inc.
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
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