Hello Sjoerd,
On Fri, Nov 14, 2014 at 8:46 PM, Sjoerd Simons
sjoerd.sim...@collabora.co.uk wrote:
Explicitly set the dr_mode for the dwc3 controller on the
Snow board to host mode. This is required to ensure the
controller is initialized in the right mode if the kernel is
build with USB
Assign the pointer to bridge ops structure(drm_bridge_funcs) in
the bridge driver itself, instead of passing it to drm_bridge_init.
This will allow bridge driver developer to pack bridge private
information inside the bridge object and pass only the drm-relevant
information to drm_bridge_init.
This patch does the following changes:
-- Use usleep_range instead of udelay.
-- Remove driver_private member from ptn3460 structure.
-- Make all possible functions and structures static.
-- Use dev_err for non-DRM errors.
-- Arrange header files
Currently, third party bridge drivers(ptn3460) are dependent
on the corresponding encoder driver init, since bridge driver
needs a drm_device pointer to finish drm initializations.
The encoder driver passes the drm_device pointer to the
bridge driver. Because of this dependency, third party
This series is based on master branch of Linus tree at:
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Changes since V2:
-- Address comments from Jingoo Han for ps8622 driver
-- Address comments from Daniel, Rob and Thierry regarding
bridge chaining
Force bridge connector detection at the end of the bridge attach.
This is needed to detect the bridge connector early.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
drivers/gpu/drm/bridge/ptn3460.c |3 +++
1 file changed, 3 insertions(+)
diff --git
Modify driver to support drm_bridge.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
.../devicetree/bindings/video/exynos_dp.txt| 12 +++
drivers/gpu/drm/exynos/exynos_dp_core.c| 37
drivers/gpu/drm/exynos/exynos_dp_core.h|1
Modify driver to support gpiod interface.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
drivers/gpu/drm/bridge/ptn3460.c | 88 --
1 file changed, 36 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/bridge/ptn3460.c
Move drm/bridge documentation to video/bridge.
Also, add proper documentation for gpios used by ptn3460.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
.../devicetree/bindings/drm/bridge/ptn3460.txt | 39
.../devicetree/bindings/video/bridge/ptn3460.txt |
Use drm_bridge helpers to modify the driver to support
i2c driver model.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
drivers/gpu/drm/bridge/Kconfig |2 +
drivers/gpu/drm/bridge/ptn3460.c| 124 +--
Define videoports and use endpoints to describe the connection between
the encoder, bridge and the panel, instead of using phandles.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
arch/arm/boot/dts/exynos5420-peach-pit.dts | 31 ++--
1 file changed, 29
Define videoports and use endpoints to describe the connection between
the encoder, bridge and the panel, instead of using phandles.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
arch/arm/boot/dts/exynos5250-snow.dts | 30 --
1 file changed, 28
ps8622 eDP-LVDS converter bridge chip is from parade technologies
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
.../devicetree/bindings/vendor-prefixes.txt|1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
From: Vincent Palatin vpala...@chromium.org
This patch adds drm_bridge driver for parade DisplayPort
to LVDS bridge chip.
Signed-off-by: Vincent Palatin vpala...@chromium.org
Signed-off-by: Andrew Bresticker abres...@chromium.org
Signed-off-by: Sean Paul seanp...@chromium.org
Signed-off-by:
Add drm_panel calls to the driver to make the panel and
bridge work together in tandem.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
.../devicetree/bindings/drm/bridge/ptn3460.txt | 12 ++
drivers/gpu/drm/bridge/Kconfig |1 +
Add documentation for DT properties supported by ps8622/ps8625
eDP-LVDS converter.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
.../devicetree/bindings/video/bridge/ps8622.txt| 31
1 file changed, 31 insertions(+)
create mode 100644
On Fri, Nov 14, 2014 at 7:13 PM, Zubair Lutfullah Kakakhel
zubair.kakak...@imgtec.com wrote:
On 14/11/14 11:08, Andy Yan wrote:
On 2014年11月14日 18:55, Zubair Lutfullah Kakakhel wrote:
On 14/11/14 10:53, Andy Yan wrote:
Hi ZubairLK:
Thanks for your review.
On 2014年11月14日 18:19, Zubair
On Sat, Nov 15, 2014 at 06:07:50PM +0800, Daniel Kurtz wrote:
On Fri, Nov 14, 2014 at 7:13 PM, Zubair Lutfullah Kakakhel
zubair.kakak...@imgtec.com wrote:
On 14/11/14 11:08, Andy Yan wrote:
On 2014年11月14日 18:55, Zubair Lutfullah Kakakhel wrote:
On 14/11/14 10:53, Andy Yan wrote:
On 13/11/14 14:13, Ezequiel Garcia wrote:
From: Phani Movva phani.mo...@imgtec.com
This commit adds support for Cosmic Circuits 10001 10-bit ADC device.
Signed-off-by: Phani Movva phani.mo...@imgtec.com
Signed-off-by: Naidu Tellapati naidu.tellap...@imgtec.com
[Ezequiel: code style
On Sat, Nov 15, 2014 at 10:12:18AM +, Russell King - ARM Linux wrote:
Once the wranglings on the patch series are complete, I do intend to test
it on the platforms I have - and remember that I do have the ALSA based
audio and CEC bits as well, some of which will probably need a little bit
On Friday 14 November 2014 15:59:02 Andrew Bresticker wrote:
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 2fb0fdf..4b931eb 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -436,4 +436,17 @@ config CRYPTO_DEV_QCE
hardware. To compile
On Friday 14 November 2014 13:59:43 Andrew Bresticker wrote:
Add support for the IMG Multi-threaded DMA Controller (MDC) found on
certain IMG SoCs. Currently this driver supports the variant present
on the MIPS-based Pistachio SoC.
Signed-off-by: Andrew Bresticker abres...@chromium.org
On Friday 14 November 2014 13:59:42 Andrew Bresticker wrote:
Add a binding document for the IMG Multi-threaded DMA Controller (MDC)
present on the MIPS-based Pistachio and other IMG SoCs.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Acked-by: Arnd Bergmann a...@arndb.de
--
To
This suspend patch is only support cut off the power of cpu and some external
devices, since we still lack power_domain driver, so the other power rail
of rk3288 need keep power on.
I have tested it on rk3288-evb board, atop next-20141112. goto suspend by type
echo mem /sys/power/state, vdd_cpu
add pmu sram node for suspend, add global_pwroff pinctrl.
The pmu sram is used to store the resume code.
global_pwroff is held low level at work, it would be pull to high
when entering suspend. reference this in the board DTS file since
some boards need it.
ddrio_pwroff is power switch of
global_pwroff would be pull to high when RK3288 entering suspend,
this pin is a sleep signal for RK808, so RK808 could goto sleep
mode, and some regulators would be disable.
Signed-off-by: Chris Zhong z...@rock-chips.com
---
Changes in v8:
- keep all except cputp power rail on during suspend
-
The pmu-sram is used to store resume code, suspend/resume need get the
address of it. Therefore add a binding and documentation for it.
Signed-off-by: Tony Xie x...@rock-chips.com
Signed-off-by: Chris Zhong z...@rock-chips.com
Reviewed-by: Doug Anderson diand...@chromium.org
---
Changes in v8:
On 11/13/2014 06:52 AM, Stanimir Varbanov wrote:
Hi Grant, Arnd and Erico
On 11/11/2014 01:07 PM, Grant Likely wrote:
On Fri, 07 Nov 2014 18:04:35 +0100
, Arnd Bergmann a...@arndb.de
wrote:
On Friday 07 November 2014 14:37:26 DATACOM - Érico Nunes wrote:
Hello Arnd and all,
On
Provide information about how to bind internal iMX6Q/DL HDMI DDC I2C
master controller. The property is set as optional one, because iMX6
HDMI DDC bus may be represented by one of general purpose I2C busses
found on SoC.
Signed-off-by: Vladimir Zapolskiy vladimir_zapols...@mentor.com
Cc: Wolfram
On 11/15/2014 07:46 AM, Jonathan Cameron wrote:
On 13/11/14 14:13, Ezequiel Garcia wrote:
From: Phani Movva phani.mo...@imgtec.com
This commit adds support for Cosmic Circuits 10001 10-bit ADC device.
Signed-off-by: Phani Movva phani.mo...@imgtec.com
Signed-off-by: Naidu Tellapati
On Fri, Nov 14, 2014 at 10:37:27AM +0530, Vignesh R wrote:
From: Brad Griffis bgrif...@ti.com
TSC interrupt handler had udelay to avoid reporting of false pen-up
interrupt to user space. This patch implements workaround suggesting in
Advisory 1.0.31 of silicon errata for am335x, thus
Am Freitag, 14. November 2014, 16:32:25 schrieb Julien CHAUVEAU:
This enables user space access to the 3 PWM available on the Radxa Rock
headers.
Signed-off-by: Julien CHAUVEAU julien.chauv...@neo-technologies.fr
added to my v3.19-armsoc/dts branch
--
To unsubscribe from this list: send the
Hi,
This series adds .dts files for Synology DS213j (armada 370 2-bay NAS) and
DS414 (armada XP 4-bay NAS) devices. It is based on comments received on
a v0 submission of DS213j .dts file [1].
Andrew, in this v1, the two .dts files are still separate w/o any common
.dtsi. I took a quick look it
This patch adds uartX labels for Armada SoC serial nodes. This is
a preliminary work to be able to easily reference the serial lines
in Device Tree files. One expected future use is when providing
stdout-path property for barebox.
Signed-off-by: Arnaud Ebalard a...@natisbad.org
---
Synology DS213j is a 2-bay NAS powered by a Marvell Armada 370
(88F6710 @1.2Ghz). It is very similar on many aspects to previous
2-bay synology models based on Marvell kirkwood SoC. Here is a
short summary of the device:
- 512MB RAM
- boot on SPI flash (64Mbit Micron N25Q064)
- 1 GbE
Synology DS414 is a 4-bay NAS powered by a Marvell Armada XP
(mv78230 dual-core @1.33Ghz). It is very similar on many aspects
to previous 4-bay synology models based on Marvell kirkwood SoC.
Here is a short summary of the device:
- 1GB RAM
- Boot on SPI flash (64Mbit Micron N25Q064)
- 2 GbE
This patch series implements a multiplatform target that runs on a
variety of different Broadcom chipsets based on the BMIPS CPUs. It
evolved out of the BMIPS updates and BCM3384 platform support
RFC posted earlier.
V1-V2:
- Add several more DTS files so the same kernel can boot on multiple
From: Dmitry Torokhov d...@chromium.org
Return value of irq_of_parse_and_map() is unsigned int, with 0
indicating failure, so testing for negative result never works.
Signed-off-by: Dmitry Torokhov d...@chromium.org
Acked-by: Florian Fainelli f.faine...@gmail.com
Tested-by: Kevin Cernekee
This will need to be called from a few different places, and the logic
is starting to get a bit hairy (with the need for IPIs, CPU bug
workarounds, and hazards).
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/kernel/smp-bmips.c | 65 +++-
1
BMIPS435x and BMIPS438x have a single shared L1 D$ and load/store unit,
so it isn't necessary to raise IPIs to keep both CPUs coherent.
BMIPS5000 has VIPT L1 caches that handle aliases in hardware, and its I$
fills from D$. But a special sequence with 2 SYNCs and 32 NOPs is needed
to ensure
On some chips like bcm3384, other stuff gets wired up to CPU1's IE_IRQ1
input, generating spurious IRQs. In this case we want the platform code
to be able to mask it off.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/include/asm/bmips.h | 1 +
arch/mips/kernel/smp-bmips.c | 6
We have a bunch of platforms using mti,cpu-interrupt-controller but
the mti prefix isn't documented. Fix this.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
Currently the driver assumes that REG_BASE+0x00 is the IRQ enable mask,
and REG_BASE+0x04 is the IRQ status mask. This is true on BCM3384 and
BCM7xxx, but it is not true for some of the controllers found on BCM63xx
chips. So we will change a couple of key assumptions:
- Don't assume that both
This hardware shows up on the newly-supported BCM3384 cable chip, as well
as several old BCM63xx DSL chips.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e5e8a55..6ab20b4 100644
---
bmips_be_defconfig supports Linux running on the following CM and DSL
SoCs:
- BCM3384 (BMIPS5000) cable modem application processor, BE, SMP
- BCM3384 (BMIPS4355) cable modem spare CPU*, BE
- BCM6328 (BMIPS4355) ADSL chip, BE
- BCM6368 (BMIPS4350) ADSL chip, BE, SMP
*experimental; most
Add myself as a maintainer for the new BMIPS target.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
MAINTAINERS | 12
1 file changed, 12 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6ab20b4..e96b4ae 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2108,6 +2108,18
BMIPS platforms can select multiple CPUs, in which case we'll need to
use the greatest common denominator (= 1 7 = 128 bytes, for the
BMIPS5000 L2).
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/Kconfig
A couple of platforms register two buses and call of_platform_populate().
Move this into a common function to reduce duplication.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/include/asm/prom.h | 1 +
arch/mips/kernel/prom.c | 18 ++
This is a dual core (quad thread) BMIPS5000. It needs a little extra
code to boot the second core (CPU2/CPU3), but for now we can treat it the
same as a single core BMIPS5000.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/include/asm/cpu.h | 1 +
arch/mips/kernel/cpu-probe.c |
The secondary CPU's reset vector needs to be set to KSEG1 for a cold
boot (release from reset), or KSEG0 for a warm restart. On a cold boot
KSEG0 may be unavailable (BMIPS4380), and on a warm restart KSEG1 may
be unavailable (XKS01 mode on 4380 or 5000).
Signed-off-by: Kevin Cernekee
CONFIG_MIPS_CPU_SCACHE determines whether to build sc-mips.c. However,
it is currently hardwired to use an L1_SHIFT of 6 (64 bytes). Move the
L1_SHIFT selection into the CPU or SoC section so that other SoCs can
select different values.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
From: Jon Fraser jfra...@broadcom.com
BMIPS3300 processors do not have the hardware to support SMP, but with a
small tweak, the SMP ebase relocation code allows BMIPS3300-based
platforms to reuse the S2/S3 power management code from BMIPS4380-based
chips. Normally this is as simple as adding one
From: Jon Fraser jfra...@broadcom.com
CPU interrupts need to be disabled on a cpu being taken down.
When a cpu is hot-plugged out of the system the following sequence occurs.
On the CPU where the hotplug sequence was initiated:
cpu_down
_cpu_down {
Commit 078a55fc824c1 (Delete __cpuinit/__CPUINIT usage from MIPS code)
removed our __CPUINIT directives, so now the .previous directives
are superfluous. Remove them.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/kernel/bmips_vec.S | 3 ---
1 file changed, 3 deletions(-)
diff
On some older BMIPS5200 (dual core / quad thread) platforms, the
PROM code set up CPU2/CPU3 so they would be started through an NMI
instead of through the ACTION register. But this was incompatible with
some power management features that were later added, so the scheme was
changed so that Linux
This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
it has the following characteristics:
- 64 to 160+ level IRQs
- Atomic set/clear registers
- Reasonably predictable register layout (N status words, then N
mask status words, then N mask set words, then N mask clear
To date, all supported controllers have had the IRQEN register at offset
0x00 and the IRQSTAT register at 0x04. So in DT we would typically see
something like:
reg = 0xf0406800 0x8;
We still want to support this format, but we also need to support cases
where IRQEN and IRQSTAT aren't
From: Dmitry Torokhov d...@chromium.org
Return value of irq_of_parse_and_map() is unsigned int, with 0
indicating failure, so testing for negative result never works.
Signed-off-by: Dmitry Torokhov d...@chromium.org
Acked-by: Florian Fainelli f.faine...@gmail.com
Tested-by: Kevin Cernekee
Several drivers now use this API, including the ARM GIC driver, so remove
the outdated comment.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
Documentation/IRQ-domain.txt | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/Documentation/IRQ-domain.txt
On Sun, Nov 16, 2014 at 01:04:12AM +0100, Arnaud Ebalard wrote:
This patch adds uartX labels for Armada SoC serial nodes. This is
a preliminary work to be able to easily reference the serial lines
in Device Tree files. One expected future use is when providing
stdout-path property for
Javier Martinez Canillas wrote:
Hello Sjoerd,
Hi,
On Fri, Nov 14, 2014 at 8:46 PM, Sjoerd Simons
sjoerd.sim...@collabora.co.uk wrote:
Explicitly set the dr_mode for the dwc3 controller on the
Snow board to host mode. This is required to ensure the
controller is initialized in the
On Sun, Nov 16, 2014 at 01:04:23AM +0100, Arnaud Ebalard wrote:
Synology DS213j is a 2-bay NAS powered by a Marvell Armada 370
(88F6710 @1.2Ghz). It is very similar on many aspects to previous
2-bay synology models based on Marvell kirkwood SoC. Here is a
short summary of the device:
-
On Sun, Nov 16, 2014 at 01:04:34AM +0100, Arnaud Ebalard wrote:
Synology DS414 is a 4-bay NAS powered by a Marvell Armada XP
(mv78230 dual-core @1.33Ghz). It is very similar on many aspects
to previous 4-bay synology models based on Marvell kirkwood SoC.
Here is a short summary of the
Hi Olof and Arnd
On Tue, Nov 11, 2014 at 7:59 PM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hello Olof and Arnd,
On Sun, Nov 9, 2014 at 9:50 AM, Abhilash Kesavan a.kesa...@samsung.com
wrote:
These were originally part of 2 patchsets[1][2] adding support for Exynos7.
The clock and
Andrew, in this v1, the two .dts files are still separate w/o any common
.dtsi. I took a quick look it seems there are small differences between
the two which make me wonder if its worth the trouble:
- DS414 fans are not handled by the SoC
- various pinctrl variations
- a tiny
+ pmx_uart0: pmx-uart0 {
+ marvell,pins = mpp0, mpp1;
+ marvell,function = uart0;
+ };
This however does not seem to be in armada-370.dtsi. This is probably
because
On Thu, Nov 13, 2014 at 1:15 PM, Ankit Jindal ankit.jin...@linaro.org wrote:
This patch adds device tree binding documentation for
X-Gene QMTM UIO driver.
Signed-off-by: Ankit Jindal ankit.jin...@linaro.org
Signed-off-by: Tushar Jagad tushar.ja...@linaro.org
---
Abhilash Kesavan wrote:
Hi Olof and Arnd
Hi
On Tue, Nov 11, 2014 at 7:59 PM, Abhilash Kesavan
kesavan.abhil...@gmail.com wrote:
Hello Olof and Arnd,
On Sun, Nov 9, 2014 at 9:50 AM, Abhilash Kesavan a.kesa...@samsung.com
wrote:
These were originally part of 2 patchsets[1][2]
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