Hi,
On 11/26/2014 07:44 PM, Maxime Ripard wrote:
On Wed, Nov 26, 2014 at 09:30:40AM +0100, Hans de Goede wrote:
Hi,
On 11/25/2014 07:04 PM, Maxime Ripard wrote:
Hi,
On Sun, Nov 23, 2014 at 01:54:39PM +0100, Hans de Goede wrote:
While working on pinctrl for the A31s, I noticed that function
Hi Liviu,
On Tuesday 11 November 2014 11:02 PM, Liviu Dudau wrote:
DT files used in the compilation phase can be preprocessed by the C
preprocessor. This requires an include/dt-bindings directory to be
present in the arch/arm64/boot/dts directory.
Signed-off-by: Liviu Dudau liviu.du...@arm.com
On Wed, 26 Nov 2014, Hans de Goede wrote:
Hi,
On 11/25/2014 05:57 PM, Lee Jones wrote:
On Sun, 23 Nov 2014, Hans de Goede wrote:
Add a driver for mod0 clocks found in the prcm. Currently there is only
one mod0 clocks in the prcm, the ir clock.
Signed-off-by: Hans de Goede
Hi,
On 11/26/2014 10:13 PM, Maxime Ripard wrote:
Hi,
On Tue, Nov 25, 2014 at 09:29:21AM +0100, Hans de Goede wrote:
Hi,
On 11/24/2014 11:03 PM, Maxime Ripard wrote:
On Fri, Nov 21, 2014 at 10:13:10AM +0100, Hans de Goede wrote:
Hi,
On 11/21/2014 09:49 AM, Maxime Ripard wrote:
Hi,
On
Hi,
On Wed, 2014-11-26 at 22:24 -0700, Lina Iyer wrote:
- compatible:
@@ -14,10 +23,13 @@ PROPERTIES
Value type: string
Definition: shall contain qcom,saw2. A more specific value should be
one of:
Which driver is supposed
On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
hongzhou.y...@mediatek.com wrote:
+* Mediatek MT65XX Pin Controller
+
+The Mediatek's Pin controller is used to control GPIO pins.
It's not GPIO pins, since they are not always general purpose. It's just
pins. Say control SoC pins.
+Required
On 11/27/2014 06:24 AM, Lina Iyer wrote:
SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The wake up for the SPM is an
Lina,
a night for me has passed and I have in the meantime 3 new versions of
the patchset obviously done in the hurry and not tested.
Furthermore the change log fails to give the details, Address review
comments on spm.c is just a clue and when I look at the spm.c code all
the comments
On 11/27/2014 01:13 AM, Lina Iyer wrote:
Add cpuidle driver interface to allow cpus to go into idle states. Use
the cpuidle DT interface, common across ARM architectures, to provide
the idle state information to the cpuidle framework.
Supported modes at this time are Standby and Standalone
On Tue, 25 Nov 2014, Arnd Bergmann wrote:
On Tuesday 25 November 2014 16:24:59 Lee Jones wrote:
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index b21f12f..e502f15 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -93,6 +93,13 @@ config
()On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
hongzhou.y...@mediatek.com wrote:
From: Hongzhou Yang hongzhou.y...@mediatek.com
The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs.
The GPIO controller have pinmux, pull enable, pull select, direction and
output
On Sun, Nov 23, 2014 at 02:38:14PM +0100, Hans de Goede wrote:
Add pinmux settings for the ir receive pin of the A31.
Signed-off-by: Hans de Goede hdego...@redhat.com
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
On Thursday 27 November 2014 09:02:55 Lee Jones wrote:
On Tue, 25 Nov 2014, Arnd Bergmann wrote:
On Tuesday 25 November 2014 16:24:59 Lee Jones wrote:
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index b21f12f..e502f15 100644
--- a/drivers/irqchip/Kconfig
+++
Hello,
finally I managed to test this series on my (unmodified) rn104.
For patch 1: Maybe point out that the issue with the century bit isn't
that critical, because this bit is not expected to be set before year 2100.
For patch 3: This patch adds a few dev_err calls that get later amended
in
On Thu, 27 Nov 2014, Arnd Bergmann wrote:
On Thursday 27 November 2014 09:02:55 Lee Jones wrote:
On Tue, 25 Nov 2014, Arnd Bergmann wrote:
On Tuesday 25 November 2014 16:24:59 Lee Jones wrote:
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index
Hi,
On Thu, Nov 27, 2014 at 4:41 PM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 11/26/2014 10:13 PM, Maxime Ripard wrote:
Hi,
On Tue, Nov 25, 2014 at 09:29:21AM +0100, Hans de Goede wrote:
Hi,
On 11/24/2014 11:03 PM, Maxime Ripard wrote:
On Fri, Nov 21, 2014 at 10:13:10AM
On Wed, Nov 26, 2014 at 10:14 PM, Dave Gerlach d-gerl...@ti.com wrote:
--- a/lib/devres.c
+++ b/lib/devres.c
@@ -72,6 +72,64 @@ void __iomem *devm_ioremap_nocache(struct device *dev,
resource_size_t offset,
EXPORT_SYMBOL(devm_ioremap_nocache);
/**
+ * devm_ioremap_exec - Managed
On Thursday 27 November 2014 09:29:01 Lee Jones wrote:
On Thu, 27 Nov 2014, Arnd Bergmann wrote:
On Thursday 27 November 2014 09:02:55 Lee Jones wrote:
On Tue, 25 Nov 2014, Arnd Bergmann wrote:
On Tuesday 25 November 2014 16:24:59 Lee Jones wrote:
diff --git
Hi,
On 27/11/14 05:29, Viresh Kumar wrote:
Hi Sudeep,
On 26 November 2014 at 22:30, Sudeep Holla sudeep.ho...@arm.com wrote:
On 26/11/14 08:46, Viresh Kumar wrote:
We only need to have one entry in cpus@cpu0 node which will match with
drivers
name.
This seems fundamentally broken as the
On Thu, 27 Nov 2014, Arnd Bergmann wrote:
On Thursday 27 November 2014 09:29:01 Lee Jones wrote:
On Thu, 27 Nov 2014, Arnd Bergmann wrote:
On Thursday 27 November 2014 09:02:55 Lee Jones wrote:
On Tue, 25 Nov 2014, Arnd Bergmann wrote:
On Tuesday 25 November 2014 16:24:59 Lee
Hi,
On 11/27/2014 10:28 AM, Chen-Yu Tsai wrote:
Hi,
On Thu, Nov 27, 2014 at 4:41 PM, Hans de Goede hdego...@redhat.com wrote:
snip
I notice that you've not responded to my proposal to simple make the clock
node a child node of the clocks node in the dt, that should work nicely, and
avoid
On Thu, Nov 27, 2014 at 09:44:42AM +0100, Linus Walleij wrote:
On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
hongzhou.y...@mediatek.com wrote:
+* Mediatek MT65XX Pin Controller
+
+The Mediatek's Pin controller is used to control GPIO pins.
It's not GPIO pins, since they are not
On 27 November 2014 at 15:24, Sudeep Holla sudeep.ho...@arm.com wrote:
No that won't suffice. You can't modify the DTs of the platforms using
cpufreq-dt.c as of today. They should continue to work, so either you
retain all the existing platform device creation in platform code as is
or do
Hi Kevin,
On Wed, Nov 26, 2014 at 07:43:01PM +, Kevin Hilman wrote:
Daniel Lezcano daniel.lezc...@linaro.org writes:
On 11/21/2014 07:03 PM, Lina Iyer wrote:
Add cpuidle driver interface to allow cpus to go into C-States. Use the
cpuidle DT interface, common across ARM architectures,
Hi Chanwoo,
On Thursday 27 November 2014 01:04 PM, Chanwoo Choi wrote:
This patch adds driver data for Exynos5433 SoC. Exynos5433 includes 228 multi-
functional input/output port pins and 135 memory port pins. There are 41 general
port groups and 2 memory port groups.
Cc: Tomasz Figa
On 27/11/14 07:35, Chanwoo Choi wrote:
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC
based on Octal core CPUs (quad Cortex-A57 and quad Cortex-A53).
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof
Hi Pankaj,
On 11/27/2014 07:26 PM, Pankaj Dubey wrote:
Hi Chanwoo,
On Thursday 27 November 2014 01:04 PM, Chanwoo Choi wrote:
This patch adds driver data for Exynos5433 SoC. Exynos5433 includes 228
multi-
functional input/output port pins and 135 memory port pins. There are 41
general
R-Car H2 (r8a7790) contains four Cortex-A15 and four Cortex-A7 cores,
hence the second interrupt specifier cell for Private Peripheral
Interrupts should use GIC_CPU_MASK_SIMPLE(8).
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
Untested.
Is this correct? Or should the interrupts be
R-Car E2 (r8a7794) contains two Cortex-A7 cores, hence the second
interrupt specifier cell for Private Peripheral Interrupts should use
GIC_CPU_MASK_SIMPLE(2).
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
Untested
---
arch/arm/boot/dts/r8a7794.dtsi | 10 +-
1 file
R-Car M2-W (r8a7791) contains two Cortex-A15 cores, hence the second
interrupt specifier cell for Private Peripheral Interrupts should use
GIC_CPU_MASK_SIMPLE(2).
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
Tested on koelsch
---
arch/arm/boot/dts/r8a7791.dtsi | 10 +-
1
R-Mobile APE6 (r8a73a4) contains four Cortex-A15 and four Cortex-A7
cores, hence the second interrupt specifier cell for Private Peripheral
Interrupts should use GIC_CPU_MASK_SIMPLE(8).
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
Untested.
Is this correct? Or should the
Hi all,
This patch series corrects the masks in the second interrupt cells for
Private Peripheral Interrupts in dtsi files for the shmobile family of
SoCs.
It's my understanding this mask should reflect the actual number of CPU
cores the interrupt is wired too.
Is that correct?
-
Hi Punnaiah,
On 11/25/2014 05:22 PM, Punnaiah Choudary Kalluri wrote:
Added EDAC support for reporting the ecc errors of synopsys ddr controller.
The ddr ecc controller corrects single bit errors and detects double bit
errors.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
2014-11-26 4:03 GMT+08:00 Greg KH gre...@linuxfoundation.org:
On Tue, Nov 25, 2014 at 08:16:58PM +0800, Chunyan Zhang wrote:
Add a full sc9836-uart driver for SC9836 SoC which is based on the
spreadtrum sharkl64 platform.
This driver also support earlycon.
Signed-off-by: Chunyan Zhang
On Wed, Nov 26, 2014 at 01:51:01PM -0800, Bjorn Andersson wrote:
This adds the missing state parameter to the call down to the RPM. This
is currently hard coded to the active state, as that's all we're
supporting at this moment.
Acked-by: Mark Brown broo...@kernel.org
signature.asc
On Wed, Nov 26, 2014 at 3:34 PM, Peter Hurley pe...@hurleysoftware.com wrote:
On 11/26/2014 08:33 AM, Grant Likely wrote:
On Tue, 25 Nov 2014 15:37:16 -0800
, Kevin Cernekee cerne...@gmail.com
wrote:
On Tue, Nov 25, 2014 at 12:34 PM, Greg KH gre...@linuxfoundation.org
wrote:
On Wed, Nov
On 27/11/14 10:22, Viresh Kumar wrote:
On 27 November 2014 at 15:24, Sudeep Holla sudeep.ho...@arm.com wrote:
No that won't suffice. You can't modify the DTs of the platforms using
cpufreq-dt.c as of today. They should continue to work, so either you
retain all the existing platform device
On Thu, Nov 27, 2014 at 07:35:13AM +, Chanwoo Choi wrote:
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC
based on Octal core CPUs (quad Cortex-A57 and quad Cortex-A53).
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Arnd Bergmann
On Thu, Nov 27, 2014 at 07:35:12AM +, Chanwoo Choi wrote:
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index f4536e0..8a5e8a0 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -152,6 +152,16 @@ config ARCH_EXYNOS
help
This enables support for Samsung
Document usage of ena-gpios properties which turn on external/GPIO
control over regulator.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
Documentation/devicetree/bindings/mfd/max77686.txt | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git
Document new properties for regulators (ena-gpios and
ena-gpio-open-drain) for enabling control over GPIO.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
Documentation/devicetree/bindings/regulator/regulator.txt | 4
1 file changed, 4 insertions(+)
diff --git
On Thu, Nov 27, 2014 at 07:34:59AM +, Chanwoo Choi wrote:
This patch add binding documentation for Exynos5433 clock controller.
Exynos5433 has various clock domains So, this documentation explains
the detailed clock domains ans usage guide.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
On 11/27/2014 08:18 PM, Catalin Marinas wrote:
On Thu, Nov 27, 2014 at 07:35:12AM +, Chanwoo Choi wrote:
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index f4536e0..8a5e8a0 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -152,6 +152,16 @@ config ARCH_EXYNOS
help
Use ena_gpio from regulator constraints (filled by parsing generic
bindings) to initialize the GPIO enable control. Support also the old
way: ena_gpio supplied in regulator_config structure.
This also adds a new set_ena_gpio() callback in regulator_ops structure
which driver may provide to
The driver is used only on Exynos based boards with DTS support.
After removal of board file support from max77686 and max77802 regulator
drivers, the MFD driver can be converted to DTS-only version. This
simplifies a little the code:
1. No dead (unused) entries in platform_data structure.
2. More
On Thu, Nov 27, 2014 at 08:34:29AM +, Pankaj Dubey wrote:
Hi Liviu,
On Tuesday 11 November 2014 11:02 PM, Liviu Dudau wrote:
DT files used in the compilation phase can be preprocessed by the C
preprocessor. This requires an include/dt-bindings directory to be
present in the
Remove fixed regulators (duplicating what max77686 provides) and
add GPIO control to max77686 regulators. Add of_compatible to
voltage-regulators node.
This gives the system full control over those regulators. Previously
the state of such regulators was a mixture of what max77686 driver set
over
Add enable control over GPIO for regulators supporting this: LDO20,
LDO21, LDO22, buck8 and buck9.
This is needed for proper (and full) configuration of the Maxim 77686
PMIC without creating redundant 'regulator-fixed' entries.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
Drivers often add custom DTS properties for parsing the GPIO for
regulator enable control. Some of them don't have to do this in a
special custom way and would work with a generic approach (e.g. S5M8767,
S2MPS1x, MAX77686). As such drivers have to do this on their own,
multiple different bindings
Hi,
The patchset generalizes the ena_gpio bindings and finally adds GPIO
support to the max77686 driver. Adding GPIO to max77686 allows removal of
fixed regulators from DTS which duplicate the description of hardware.
Rationale behind adding ena-gpios to regulator core
Dear Mark,
On 11/27/2014 08:21 PM, Mark Rutland wrote:
On Thu, Nov 27, 2014 at 07:34:59AM +, Chanwoo Choi wrote:
This patch add binding documentation for Exynos5433 clock controller.
Exynos5433 has various clock domains So, this documentation explains
the detailed clock domains ans usage
On Thu, Nov 27, 2014 at 4:29 PM, Michal Simek michal.si...@xilinx.com wrote:
Hi Punnaiah,
On 11/25/2014 05:22 PM, Punnaiah Choudary Kalluri wrote:
Added EDAC support for reporting the ecc errors of synopsys ddr controller.
The ddr ecc controller corrects single bit errors and detects double
2014-11-26 17:48 GMT+08:00 Tobias Klauser tklau...@distanz.ch:
On 2014-11-25 at 13:16:58 +0100, Chunyan Zhang chunyan.zh...@spreadtrum.com
wrote:
---
[...]
+
+config SERIAL_SPRD_CONSOLE
+bool SPRD UART console support
+depends on SERIAL_SPRD=y
+select
On Tue, Nov 25, 2014 at 12:16:54PM +, Chunyan Zhang wrote:
The file of-serial.txt was only for 8250 compatible UART implementations,
so renamed it to 8250.txt to avoid confusing other persons.
This is recommended by Arnd, see:
On Thursday 27 November 2014 16:35:08 Chanwoo Choi wrote:
+ - samsung,exynos5433-cmu-bus0, samsung,exynos5433-cmu-bus1
+and samsung,exynos5433-cmu-bus2 - clock controller compatible for
CMU_BUS
+which generates global data buses clock and global peripheral buses
clock.
- reg:
This is a new driver which controls the SPI component of ST's
Synchronous Serial Controller (SSC).
Lee Jones (4):
spi: Add new driver for STMicroelectronics' SPI Controller
spi: st: Provide Device Tree binding documentation
ARM: sti: Provide DT nodes for SSC[0..4]
ARM: sti: Provide DT
The Synchronous Serial Controller is used to provide SPI.
These are the ports which are located on the Stand-By Controller (SBC).
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
arch/arm/boot/dts/stih407.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git
The Synchronous Serial Controller is used to provide SPI.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
arch/arm/boot/dts/stih407.dtsi | 54 ++
1 file changed, 54 insertions(+)
diff --git a/arch/arm/boot/dts/stih407.dtsi
This patch adds support for the SPI portion of ST's SSC device.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/spi/Kconfig | 8 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-st.c | 535 +++
3 files changed, 544 insertions(+)
create
This patch adds DT documentation for the SPI portion of ST's SSC device.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
Documentation/devicetree/bindings/spi/spi-st.txt | 40
1 file changed, 40 insertions(+)
create mode 100644
On Thursday 27 November 2014 16:34:58 Chanwoo Choi wrote:
+
+/*
+ * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
+ * four gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos5433_pin_ctrl[] = {
+ {
+ /* pin-controller
Hi Chanwoo,
On Thursday 27 November 2014 01:05 PM, Chanwoo Choi wrote:
This patch adds the support for CMU (Clock Management Units) of Exynos5433
which is 64bit SoC and has Octa-cores. This patch supports necessary clocks
for kernel boot as following:
- PLL/MMC/UART/MCT/I2C/SPI
Cc: Sylwester
On Tue, Nov 25, 2014 at 12:16:56PM +, Chunyan Zhang wrote:
From: Zhizhou Zhang zhizhou.zh...@spreadtrum.com
Adds the device tree support for Spreadtrum SC9836 SoC which is based on
Sharkl64 platform.
Sharkl64 platform contains the common nodes of Spreadtrum's arm64-based SoCs.
Dear Arnd,
On 11/27/2014 08:41 PM, Arnd Bergmann wrote:
On Thursday 27 November 2014 16:35:08 Chanwoo Choi wrote:
+ - samsung,exynos5433-cmu-bus0, samsung,exynos5433-cmu-bus1
+and samsung,exynos5433-cmu-bus2 - clock controller compatible for
CMU_BUS
+which generates global data
2014-11-27 2:29 GMT+08:00 Murali Karicheri m-kariche...@ti.com:
On 11/25/2014 07:16 AM, Chunyan Zhang wrote:
Add a full sc9836-uart driver for SC9836 SoC which is based on the
+#includelinux/clk.h
How about sorting this includes? asm/irq.h go first followed linux/ in
alphabatical order?
Hi,
On Tue, Nov 25, 2014 at 12:16:53PM +, Chunyan Zhang wrote:
Spreadtrum is a rapid growing chip vendor providing smart phone total
solutions.
Sharkl64 Platform is nominated as a SoC infrastructure that supports 4G/3G/2G
standards based on ARMv8 multiple core architecture.Now we have
Hi,
here's providing ath10k calibration data via device tree support which
Toshi and me have been working on. Please review.
Device tree maintainers: please review the bindings document
carefully, this is the first time I have written one.
v4:
* use correct devicetree mailing list address
v3:
From: Toshi Kikuchi tos...@chromium.org
This patch adds support for reading calibration data from Device Tree.
It looks for the calibration data in Device Tree if it can't find it
in a file. If there's no node in Device Tree, ath10k will try to find the
calibration data from OTP.
The node for
2014-11-27 19:38 GMT+08:00 Mark Rutland mark.rutl...@arm.com:
On Tue, Nov 25, 2014 at 12:16:54PM +, Chunyan Zhang wrote:
The file of-serial.txt was only for 8250 compatible UART implementations,
so renamed it to 8250.txt to avoid confusing other persons.
This is recommended by Arnd, see:
Document how calibration data can be provided to ath10k via Device Tree.
Signed-off-by: Kalle Valo kv...@qca.qualcomm.com
---
.../bindings/net/wireless/qcom,ath10k.txt | 30
1 file changed, 30 insertions(+)
create mode 100644
Hi,
On 27/11/14 12:56, Chanwoo Choi wrote:
On 11/27/2014 08:41 PM, Arnd Bergmann wrote:
On Thursday 27 November 2014 16:35:08 Chanwoo Choi wrote:
+ - samsung,exynos5433-cmu-bus0, samsung,exynos5433-cmu-bus1
+and samsung,exynos5433-cmu-bus2 - clock controller compatible for
CMU_BUS
On Thu, Nov 27, 2014 at 11:50:43AM +, Mark Rutland wrote:
On Tue, Nov 25, 2014 at 12:16:56PM +, Chunyan Zhang wrote:
+
+ timer {
+ compatible = arm,armv8-timer;
+ interrupts = 1 13 0xff01,
+1 14 0xff01,
+
2014-11-27 20:45 GMT+09:00 Arnd Bergmann a...@arndb.de:
On Thursday 27 November 2014 16:34:58 Chanwoo Choi wrote:
+
+/*
+ * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
+ * four gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl
Hi Sylwester,
On 11/27/2014 09:12 PM, Sylwester Nawrocki wrote:
Hi,
On 27/11/14 12:56, Chanwoo Choi wrote:
On 11/27/2014 08:41 PM, Arnd Bergmann wrote:
On Thursday 27 November 2014 16:35:08 Chanwoo Choi wrote:
+ - samsung,exynos5433-cmu-bus0, samsung,exynos5433-cmu-bus1
+and
On Wed, Nov 26, 2014 at 09:48:47PM +, Andrew Lunn wrote:
On Wed, Nov 26, 2014 at 09:07:33PM +, Grant Likely wrote:
On Wed, Nov 26, 2014 at 6:30 PM, Andrew Lunn and...@lunn.ch wrote:
On Wed, Nov 26, 2014 at 05:40:40PM +, Leif Lindholm wrote:
Support specifying console options
On Wed, Nov 26, 2014 at 5:32 PM, Kim, Milo milo@ti.com wrote:
(Looping backlight class subsystem maintainers)
Hi Sean,
Thanks for checking this. I'd like to describe why the original code is
preferred.
The original code is copying the values of the lp855x platform data from the
DT in
On Wed, Nov 26, 2014 at 5:32 PM, Kim, Milo milo@ti.com wrote:
(Looping backlight class subsystem maintainers)
Hi Sean,
Please see my comments below. Thanks!
On 11/27/2014 4:11 AM, Sean Paul wrote:
This patch adds a supply regulator to the lp855x platform data to
facilitate
powering
On Thursday 27 November 2014 14:08:56 Kalle Valo wrote:
diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt
b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt
new file mode 100644
index ..edefc26c6204
--- /dev/null
+++
On Thursday 27 November 2014 21:14:59 Tomasz Figa wrote:
my impression is that with the
move to arm64, you should come up with a new binding that can fully
describe each controller so you don't have to add new code and bindings
for each future SoC that uses the same scheme.
Still, this
On Thursday 27 November 2014 13:12:08 Sylwester Nawrocki wrote:
On 27/11/14 12:56, Chanwoo Choi wrote:
On 11/27/2014 08:41 PM, Arnd Bergmann wrote:
On Thursday 27 November 2014 16:35:08 Chanwoo Choi wrote:
+ - samsung,exynos5433-cmu-bus0, samsung,exynos5433-cmu-bus1
+and
Hi Lee,
snip
+static int spi_st_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev-dev.of_node;
+ struct device *dev = pdev-dev;
+ struct spi_master *master;
+ struct resource *res;
+ struct spi_st *spi_st;
+ int num_cs, cs_gpio, i, ret = 0;
+
Hi Pankaj,
On 11/27/2014 08:48 PM, Pankaj Dubey wrote:
Hi Chanwoo,
On Thursday 27 November 2014 01:05 PM, Chanwoo Choi wrote:
This patch adds the support for CMU (Clock Management Units) of Exynos5433
which is 64bit SoC and has Octa-cores. This patch supports necessary clocks
for kernel
On Thursday 27 November 2014 19:59:46 Lyra Zhang wrote:
2014-11-27 2:29 GMT+08:00 Murali Karicheri m-kariche...@ti.com:
On 11/25/2014 07:16 AM, Chunyan Zhang wrote:
Add a full sc9836-uart driver for SC9836 SoC which is based on the
+#includelinux/clk.h
How about sorting this
Dear Arnd,
On 11/27/2014 09:35 PM, Arnd Bergmann wrote:
On Thursday 27 November 2014 13:12:08 Sylwester Nawrocki wrote:
On 27/11/14 12:56, Chanwoo Choi wrote:
On 11/27/2014 08:41 PM, Arnd Bergmann wrote:
On Thursday 27 November 2014 16:35:08 Chanwoo Choi wrote:
+ -
On Thu, Nov 27, 2014 at 11:43:53AM +, Lee Jones wrote:
+config SPI_ST
+ tristate STMicroelectronics SPI SSC-based driver
Please select a more specific symbol, I bet ST already have other sPI
controllers. Based on the descripton SPI_ST_SSC might work.
+ depends on ARCH_STI
On Thu, Nov 27, 2014 at 11:43:54AM +, Lee Jones wrote:
+Required properties:
+- compatible : st,comms-ssc-spi or st,comms-ssc4-spi
What do the two different compatible strings mean (for example, should
ssc4 be used for version 4 and higher or is it just a quirk for that
version)?
On Thu, Nov 27, 2014 at 12:20:47PM +0100, Krzysztof Kozlowski wrote:
The driver is used only on Exynos based boards with DTS support.
After removal of board file support from max77686 and max77802 regulator
drivers, the MFD driver can be converted to DTS-only version. This
simplifies a little
On czw, 2014-11-27 at 13:03 +, Mark Brown wrote:
On Thu, Nov 27, 2014 at 12:20:47PM +0100, Krzysztof Kozlowski wrote:
The driver is used only on Exynos based boards with DTS support.
After removal of board file support from max77686 and max77802 regulator
drivers, the MFD driver can be
On Thursday 27 November 2014 21:58:53 Chanwoo Choi wrote:
Dear Arnd,
On 11/27/2014 09:35 PM, Arnd Bergmann wrote:
On Thursday 27 November 2014 13:12:08 Sylwester Nawrocki wrote:
On 27/11/14 12:56, Chanwoo Choi wrote:
On 11/27/2014 08:41 PM, Arnd Bergmann wrote:
On Thursday 27 November
On Thu, Nov 27, 2014 at 12:15:43PM +, Mark Rutland wrote:
On Wed, Nov 26, 2014 at 09:48:47PM +, Andrew Lunn wrote:
On Wed, Nov 26, 2014 at 09:07:33PM +, Grant Likely wrote:
On Wed, Nov 26, 2014 at 6:30 PM, Andrew Lunn and...@lunn.ch wrote:
On Wed, Nov 26, 2014 at 05:40:40PM
On Fri, Nov 14, 2014 at 11:52 AM, Michal Simek michal.si...@xilinx.com wrote:
The driver provide memory allocator which can
be used by others drivers to allocate memory inside OCM.
All location for 64kB blocks are supported
Allocation?
and driver is trying to allocate the largest continuous
Instead of enabling/disabling clocks at several locations in the driver,
use the runtime_pm framework. This consolidates the actions for
runtime PM in the appropriate callbacks and makes the driver more
readable and mantainable.
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
On 27/11/14 05:11, Jassi Brar wrote:
On 26 November 2014 at 22:08, Sudeep Holla sudeep.ho...@arm.com wrote:
On 26/11/14 16:20, Jassi Brar wrote:
On 26 November 2014 at 19:30, Sudeep Holla sudeep.ho...@arm.com wrote:
On 26/11/14 05:37, Jassi Brar wrote:
It seems you still
On 11/27/2014 12:43 PM, Lee Jones wrote:
This patch adds support for the SPI portion of ST's SSC device.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/spi/Kconfig | 8 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-st.c | 535
On Fri, Nov 14, 2014 at 4:21 PM, Thomas Petazzoni
thomas.petazz...@free-electrons.com wrote:
This commit adds the implementation of -suspend() and -resume()
platform_driver hooks in order to save and restore the state of the
GPIO configuration. In order to achieve that, additional fields are
On Tue, 2014-11-25 at 16:04 +0800, Yingjoe Chen wrote:
Add sysirq settings for mt6589/mt8135/mt8127
This also correct timer interrupt flag. The old setting works
because boot loader already set polarity for timer interrupt.
Without intpol support, the setting was not changed so gic
can get
On Wed, Nov 26, 2014 at 9:48 PM, Andrew Lunn and...@lunn.ch wrote:
On Wed, Nov 26, 2014 at 09:07:33PM +, Grant Likely wrote:
On Wed, Nov 26, 2014 at 6:30 PM, Andrew Lunn and...@lunn.ch wrote:
On Wed, Nov 26, 2014 at 05:40:40PM +, Leif Lindholm wrote:
Support specifying console
On Thu, Nov 27, 2014 at 01:16:36PM +, Leif Lindholm wrote:
On Thu, Nov 27, 2014 at 12:15:43PM +, Mark Rutland wrote:
On Wed, Nov 26, 2014 at 09:48:47PM +, Andrew Lunn wrote:
On Wed, Nov 26, 2014 at 09:07:33PM +, Grant Likely wrote:
On Wed, Nov 26, 2014 at 6:30 PM, Andrew
On Thu, Nov 27, 2014 at 12:12:15PM +, Catalin Marinas wrote:
On Thu, Nov 27, 2014 at 11:50:43AM +, Mark Rutland wrote:
On Tue, Nov 25, 2014 at 12:16:56PM +, Chunyan Zhang wrote:
+
+ timer {
+ compatible = arm,armv8-timer;
+ interrupts =
On Sun, Nov 16, 2014 at 9:14 PM, Beniamino Galvani b.galv...@gmail.com wrote:
Add device tree bindings documentation for Amlogic Meson pin and GPIO
controller.
Signed-off-by: Beniamino Galvani b.galv...@gmail.com
This is exactly how I want modern pin controller bindings to look
when
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