On 03/01/2015 05:00 AM, Paul Bolle wrote:
On Tue, 2015-02-24 at 10:29 +0900, Jaewon Kim wrote:
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 994793d..555e436 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -212,6 +212,15 @@ config BATTERY_MAX17042
On Saturday 28 February 2015 09:47:01 Chanwoo Choi wrote:
earlycon=exynos4210,0x14C2 is correct bootparam. You can check
it on Documentation/kernel-parameters.txt as following.
exynos4210,addr
Use early console provided by serial driver available
on
This adds support for Vybrid's interrupt router. On VF6xx models,
almost all peripherals can be used by either of the two CPU's,
the Cortex-A5 or the Cortex-M4. The interrupt router routes the
peripheral interrupts to the configured CPU.
This IRQ chip driver configures the interrupt router to
Add the Miscellaneous System Control Module (MSCM) to the base
device tree for Vybrid SoC's. This module contains registers
to get information of the individual and current (accessing)
CPU. In a second block, there is an interrupt router, which
handles the routing of the interrupts between the two
Add binding documentation for CPU configuration and interrupt router
submodule of the Miscellaneous System Control Module. The MSCM is
used in all variants of Freescale Vybrid SoC's.
Acked-by: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Stefan Agner ste...@agner.ch
---
So far the MSCM interrupt router was initialized by the boot loader
and configured all interrupts for the Cortex-A5 CPU. There are two
use cases where a proper driver is necessary:
- To run Linux on the Cortex-M4. When the kernel is running on the
non-preconfigured CPU, the interrupt router need
Hello,
Here's the fifth, latest and greatest version of the Xilinx FPGA Video IP
Cores kernel drivers.
I won't detail in great lengths the Xilinx Video IP architecture here, as that
would result in dozens of pages of documentation. The interested reader can
refer to the Zynq ZC702 Base TRD
On 3/2/2015 5:06 AM, Guennadi Liakhovetski wrote:
Hi Josh,
Thanks for a patch update. I think it looks good as a first step in your
patch series, just a minor comment below:
On Tue, 10 Feb 2015, Josh Wu wrote:
In async probe, there is a case that ov2640 is probed before the
host device which
The TPG generates multiple static or dynamic test patterns. The driver
currently hardcodes the pattern to the moving box pattern.
Signed-off-by: Christian Kohn christian.k...@xilinx.com
Signed-off-by: Hyun Kwon hyun.k...@xilinx.com
Signed-off-by: Laurent Pinchart laurent.pinch...@ideasonboard.com
Hi Kevin,
On 11/24/2014 06:36 PM, Kevin Cernekee wrote:
If an earlycon (stdout-path) node is being used, check for big-endian
or native-endian properties and pass the appropriate iotype to the
driver.
Note that LE sets UPIO_MEM (8-bit) but BE sets UPIO_MEM32BE (32-bit). The
big-endian
On 03/01/2015 05:03 AM, Paul Bolle wrote:
On Tue, 2015-02-24 at 10:29 +0900, Jaewon Kim wrote:
diff --git a/drivers/power/max77843_charger.c
b/drivers/power/max77843_charger.c
new file mode 100644
index 000..392eebc1a
--- /dev/null
+++ b/drivers/power/max77843_charger.c
@@ -0,0 +1,508
Xilinx platforms have no hardwired video capture or video processing
interface. Users create capture and memory to memory processing
pipelines in the FPGA fabric to suit their particular needs, by
instantiating video IP cores from a large library.
The Xilinx Video IP core is a framework that
The Video Timing Controller (VTC) includes a timing detector and/or a
timing generator. Only the generator is currently supported.
Signed-off-by: Laurent Pinchart laurent.pinch...@ideasonboard.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
Acked-by: Hans Verkuil hans.verk...@cisco.com
In async probe, there is a case that ov2640 is probed before the
host device which provided 'mclk'.
To support this async probe, we will get 'mclk' at first in the probe(),
if failed it will return -EPROBE_DEFER. That will let ov2640 wait for
the host device probed.
Signed-off-by: Josh Wu
Hi Josh,
Thanks for a patch update. I think it looks good as a first step in your
patch series, just a minor comment below:
On Tue, 10 Feb 2015, Josh Wu wrote:
In async probe, there is a case that ov2640 is probed before the
host device which provided 'mclk'.
To support this async probe, we
PopMetal is a rockchip rk3288 based board made by ChipSpark,
which has many interface such as VGA,HDMI,usb,ir,sdcad and lots of
sensors such as gyroscope(L3G4200D),accelerometer(mma8452),compass(AK8963C).
http://wiki.chipspark.com/en/index.php?title=PopMetal
This patch add basic support for it,
PopMetal board is a rk3288 based board made by ChipSpark, this
add root compatible property for it
Signed-off-by: Andy Yan andy@rock-chips.com
---
Changes in v2:
- change PopMetal PopMetal-RK3288 board to ChipSPARK PopMetal-RK3288 board
Documentation/devicetree/bindings/arm/rockchip.txt |
PopMetal is a rockchip rk3288 based board made by ChipSpark,
which has many interface such as VGA,HDMI,usb,ir,sdcad and lots of
sensors such as gyroscope(L3G4200D),accelerometer(mma8452),
compass(AK8963C).
This patch add a basic support for this board, which make the board
boot into a initramfs
Hi Linus,
I'd like to move forward with this patch, could you please comment on my reply
?
On Wednesday 04 February 2015 11:53:34 Laurent Pinchart wrote:
On Wednesday 04 February 2015 09:40:48 Linus Walleij wrote:
On Tue, Jan 27, 2015 at 9:31 PM, Laurent Pinchart wrote:
The function, pins
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The cpufreq driver for Tegra124 will be a different one than the old
Tegra20 cpufreq driver (tegra-cpufreq), which does not use the device
tree.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also provides automatic CPU rail voltage scaling as well. The DFLL
is a separate IP block from the usual Tegra124 clock-and-reset
controller, so it gets its own node in the
Hi
On Fri, 27 Feb 2015, Vignesh R wrote:
From: Poddar, Sourav sourav.pod...@ti.com
This patch adds hwmod data for hdq/1w driver on AM43xx.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
[vigne...@ti.com: Ported patch to v4.0-rc1]
Signed-off-by: Vignesh R vigne...@ti.com
---
On Fri, Feb 27, 2015 at 02:30:16PM -0800, Bjorn Andersson wrote:
Add binding documentation for the Qualcomm Hardware Mutex.
Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
---
Looks fine.
Reviewed-by: Andy Gross agr...@codeaurora.org
--
Qualcomm Innovation Center, Inc.
The
HI Dmitry,
On 28/02/2015 02:49, Dmitry Torokhov wrote:
On Thu, Feb 26, 2015 at 11:49:36AM +0900, Jaewon Kim wrote:
Hi Dmitry,
On 26/02/2015 10:23, Dmitry Torokhov wrote:
Hi Jaewon,
On Tue, Feb 24, 2015 at 10:29:07AM +0900, Jaewon Kim wrote:
+static void max77843_haptic_play_work(struct
Fix PM does not work on the at91sam9g20ek board
---8---
at91_pm_sram_init: failed to find sram device!
---8---
Signed-off-by: Wenyou Yang wenyou.y...@atmel.com
---
arch/arm/boot/dts/at91sam9260.dtsi |9 +++--
arch/arm/boot/dts/at91sam9g20.dtsi |9 +
2 files changed, 12
Remove the duplicate of_changeset_init. In of_selftest_changeset
testcase, the struct of_changeset chgset is initialized twice,
but only once is enough. so, drop the first initializtion code.
Signed-off-by: Wang Long long.wangl...@huawei.com
---
drivers/of/unittest.c | 1 -
1 file changed, 1
Hi Jacek
On 2015년 02월 27일 17:42, Jacek Anaszewski wrote:
Hi Ingi,
On 02/27/2015 02:01 AM, Ingi Kim wrote:
This patch supports KTD2692 flash LED driver
Ingi Kim (3):
of: Add vendor prefix for Kinetic technologies
leds: ktd2692: add device tree bindings for ktd2692
leds: Add
On Sat, 28 Feb 2015, Paul Bolle wrote:
On Wed, 2015-02-25 at 13:52 +, Lee Jones wrote:
Reviewed-by: Guenter Roeck li...@roeck-us.net
Signed-off-by: David Paris david.pa...@st.com
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/watchdog/Kconfig | 13 ++
On Sat, 28 Feb 2015, Charles Keepax wrote:
From: Richard Fitzgerald r...@opensource.wolfsonmicro.com
Signed-off-by: Richard Fitzgerald r...@opensource.wolfsonmicro.com
Signed-off-by: Charles Keepax ckee...@opensource.wolfsonmicro.com
---
drivers/mfd/arizona-core.c |3 +++
1 files
On Sat, 28 Feb 2015, Charles Keepax wrote:
Signed-off-by: Charles Keepax ckee...@opensource.wolfsonmicro.com
---
drivers/mfd/arizona-core.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
Same here. Requires DT/Clk Ack.
diff --git a/drivers/mfd/arizona-core.c
Hi Lee,
On Mon, 23 Feb 2015, Peter Griffin wrote:
Hi Lee,
I noticed you sent another version, but I didn't see a reply on this point
below.
As your now doing a re-spin for Pauls comments, I thought I would send a
reminder
just in case you hadn't seen it.
regards,
Peter.
snip
On 02/28/2015 06:00 PM, Paul Bolle wrote:
On Tue, 2015-02-24 at 16:21 +0200, Peter Ujfalusi wrote:
The DRA7x has more peripherals with DMA requests than the sDMA can handle:
205 vs 127. All DMA requests are routed through the DMA crossbar, which can
be configured to route selected incoming DMA
From: Pavel Machek pa...@ucw.cz
N900 audio recording needs that codec provides bias voltage for integrated
digital microphone and headset microphone depending which one is used.
Digital microphone uses 2 V bias and it comes from the codec A part. Codec
B part drives the headset microphone bias
В Sun, 01 Mar 2015 20:59:13 +0300
Sergei Shtylyov sergei.shtyl...@cogentembedded.com пишет:
On 3/1/2015 7:06 PM, Roman Volkov wrote:
Since WM8650 has the same 'WMT' SDHC controller as WM8505, and the
driver is already in the kernel, this node enables the controller
support for WM8650
On Sunday 01 March 2015 19:06:45 Roman Volkov wrote:
This patch set enables SD controller support for WM8650 and
fixes minor errors in WM8505 Device Tree file.
Changes in v3:
1. Add minor fixes for WM8505 SDHC node
Tested on both WM8505 and WM8650.
Roman Volkov (2):
dts: vt8500: Add
Specify the fifo sizes of the 4 uart channels on exynos7 via dt.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
arch/arm64/boot/dts/exynos/exynos7.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
Patch 1 specifies the fifo sizes for UART channels on exnyos7. Without
this the 4210 compatible defaults will be picked up which are different
from that on exynos7.
Patch 2 is based on a patch from Liviu Dudau fixing a similar issue
for arm boards.
Patch 3 is needed to enable support for arm64
According to datasheet, the registers space of SDHC controller is 1Kb,
not '0x1000', the correct value should be '0x400'. Bracket interrupt
numbers individually per recommendations.
Signed-off-by: Roman Volkov rvol...@v1ros.org
---
arch/arm/boot/dts/wm8505.dtsi | 4 ++--
1 file changed, 2
This patch set enables SD controller support for WM8650 and
fixes minor errors in WM8505 Device Tree file.
Changes in v3:
1. Add minor fixes for WM8505 SDHC node
Tested on both WM8505 and WM8650.
Roman Volkov (2):
dts: vt8500: Add SDHC node to DTS file for WM8650
dts: vt8500: Fix errors in
Since WM8650 has the same 'WMT' SDHC controller as WM8505, and the driver
is already in the kernel, this node enables the controller support for
WM8650
Signed-off-by: Roman Volkov rvol...@v1ros.org
Reviewed-by: Alexey Charkov alch...@gmail.com
---
arch/arm/boot/dts/wm8650.dtsi | 9 +
1
From: Alim Akhtar alim.akh...@samsung.com
Enable Exynos7 SOC in the arm64 defconfig. Also enable the
samsung serial driver needed by this SoC.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
arch/arm64/configs/defconfig | 4
1
Fix the exynos7 device tree to indicate that the arm generic timers
provide an active low interrupt output. Also, update the CPU mask to
match the number of CPUs on the SoC.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
arch/arm64/boot/dts/exynos/exynos7.dtsi | 9 +
1 file
Support for devicetree serial consoles via 'stdout-path' causes
bootconsoles to be disabled when the vt dummy console loads, since
there is no preferred console (the preferred console is not added
until the device is probed).
Ensure there is at least a preferred console, even if never matched.
[ +cc devicetree, Mark Rutland, Grant Likely ]
On 02/26/2015 09:58 AM, Rob Herring wrote:
On Thu, Feb 26, 2015 at 8:48 AM, Peter Hurley pe...@hurleysoftware.com
wrote:
Hi Rob,
On 02/24/2015 03:20 PM, Rob Herring wrote:
On Tue, Feb 24, 2015 at 1:53 PM, Peter Hurley pe...@hurleysoftware.com
On 3/1/2015 7:06 PM, Roman Volkov wrote:
Since WM8650 has the same 'WMT' SDHC controller as WM8505, and the driver
is already in the kernel, this node enables the controller support for
WM8650
Signed-off-by: Roman Volkov rvol...@v1ros.org
Reviewed-by: Alexey Charkov alch...@gmail.com
---
В Sun, 01 Mar 2015 20:52:55 +0100
Arnd Bergmann a...@arndb.de пишет:
On Sunday 01 March 2015 19:06:45 Roman Volkov wrote:
This patch set enables SD controller support for WM8650 and
fixes minor errors in WM8505 Device Tree file.
Changes in v3:
1. Add minor fixes for WM8505 SDHC node
This patch set enables SD controller support for WM8650 and
fixes minor errors in WM8505 Device Tree file.
Changes in v3:
1. Add minor fixes for WM8505 SDHC node
Tested on both WM8505 and WM8650.
Roman Volkov (2):
dts: vt8500: Add SDHC node to DTS file for WM8650
dts: vt8500: Fix errors in
Hello.
On 03/01/2015 10:49 PM, Roman Volkov wrote:
Since WM8650 has the same 'WMT' SDHC controller as WM8505, and the
driver is already in the kernel, this node enables the controller
support for WM8650
Signed-off-by: Roman Volkov rvol...@v1ros.org
Reviewed-by: Alexey Charkov
According to datasheet, the registers space of SDHC controller is 1Kb,
not '0x1000', the correct value should be '0x400'. Bracket interrupt
numbers individually per recommendations.
Signed-off-by: Roman Volkov rvol...@v1ros.org
---
arch/arm/boot/dts/wm8505.dtsi | 4 ++--
1 file changed, 2
Since WM8650 has the same 'WMT' SDHC controller as WM8505, and the driver
is already in the kernel, this node enables the controller support for
WM8650
Signed-off-by: Roman Volkov rvol...@v1ros.org
Reviewed-by: Alexey Charkov alch...@gmail.com
---
arch/arm/boot/dts/wm8650.dtsi | 9 +
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