On Thu, May 21, 2015 at 09:51:11AM +0200, Rafał Miłecki wrote:
On 20 May 2015 at 20:40, Brian Norris computersforpe...@gmail.com wrote:
On Wed, May 20, 2015 at 08:39:06AM +0200, Rafał Miłecki wrote:
On 20 May 2015 at 02:34, Brian Norris computersforpe...@gmail.com wrote:
On Sun, May 17,
On Tue, May 26, 2015 at 05:41:44PM -0700, Brian Norris wrote:
+ linux,part-probe = ofpart, bcm47xxpart;
^ NAK to this line. You still haven't documented any semantics for this
property. And I gave you several comments on your previous patch about
what would need to change
On Sun, May 24, 2015 at 08:32:29PM +0200, Hauke Mehrtens wrote:
This adds the NAND flash chip description for a standard chip found
connected to this SoC. This makes use of generic Broadcom NAND driver
with the iProc interface.
Signed-off-by: Hauke Mehrtens ha...@hauke-m.de
---
This
On Fri, May 22, 2015 at 07:14:25PM +0200, Gary Bisson wrote:
This series adds the Okaya 7 LCD display that is a WVGA (800x480) panel with
a 18-bit parallel interface for both Nitrogen and Sabrelite.
A U-Boot script to configure the displays based on detection of the
touch controller is
Hi Linus,
On Wed, May 13, 2015 at 1:59 AM, Linus Walleij linus.wall...@linaro.org wrote:
On Tue, May 12, 2015 at 9:38 PM, Gregory Fong gregory.0...@gmail.com wrote:
On Tue, May 12, 2015 at 3:59 AM, Linus Walleij linus.wall...@linaro.org
wrote:
On Wed, May 6, 2015 at 10:37 AM, Gregory Fong
Hanjun Guo wrote:
I don't agree with this. The GTDT should be parsed even if there's no
watchdog driver compiled for this kernel. There are no other #ifdefs in
this file.
So what's the point of parse GTDT and alloc memories for it if there
is no watchdog driver compiled for the kernel?
I
On Thu, May 21, 2015 at 04:22:31PM +0800, YH Huang wrote:
On Mon, 2015-05-18 at 11:42 +0800, Daniel Kurtz wrote:
On Mon, May 11, 2015 at 5:26 PM, YH Huang yh.hu...@mediatek.com wrote:
Add display PWM driver support to modify backlight for MT8173/MT6595.
Signed-off-by: YH Huang
Hi,
On Saturday 23 May 2015 01:24 AM, Rob Herring wrote:
On Thu, May 21, 2015 at 7:51 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
On Thursday 21 May 2015 06:15 PM, Kishon Vijay Abraham I wrote:
Hi,
On Thursday 14 May 2015 04:18 AM, Rob Herring wrote:
Add PHY driver for the Marvell
Hi Scott,
Eduardo indicated that calibration property should add fsl prefix.
I updated the patch.
Any other comments?
If not I will send V3 soon.
Thanks.
---
Best Regards,
Hongtao
-Original Message-
From: Jia Hongtao [mailto:hongtao@freescale.com]
Sent: Wednesday, April 15,
On Thu, May 21, 2015 at 03:12:53PM +0800, James Liao wrote:
From: Sascha Hauer s.ha...@pengutronix.de
On the MT8173 the clocks are provided by different units. To enable
the critical clocks we must be sure that all parent clocks are already
registered, otherwise the parents of the critical
On Wed, 2015-04-15 at 16:35 +0300, Ivan T. Ivanov wrote:
On recent Qualcomm platforms VBUS and ID lines are not routed to
USB PHY LINK controller. Use extcon framework to receive connect
and disconnect ID and VBUS notification.
Signed-off-by: Ivan T. Ivanov iva...@linaro.org
---
Changes
On Monday 25 May 2015 14:10:37 Jingoo Han wrote:
'pp-root_bus_nr' is initialized as '-1' at some soc-specific drivers
However, 'sys-busnr' is set as '0, 1, 2 ...' by pcibios_init_hw()
in arch/arm/kernel/bios32.c. '0, 1, 2 ...' means the number of
each host controller.
So, without setting
Hello Greg
Sorry for the mess. I did not want to spam the mailing list too much.
Repacking and resending. Thanks!
On Sun, May 24, 2015 at 9:29 PM, Greg Kroah-Hartman
gre...@linuxfoundation.org wrote:
On Fri, May 15, 2015 at 01:52:10PM +0200, Ricardo Ribalda Delgado wrote:
On Thu, May 21, 2015 at 03:12:52PM +0800, James Liao wrote:
The size of clk_data should be the same as CLK_APMIXED_NR_CLK
instead of ARRAY_SIZE(plls). CLK_APMIXED_* is numbered from 1, so
CLK_APMIXED_NR_CLK will be greater than ARRAY_SIZE(plls).
Signed-off-by: James Liao
Hi Fu Wei,
Some minor comments inline.
On 2015年05月25日 18:03, fu@linaro.org wrote:
From: Fu Wei fu@linaro.org
Parse SBSA Generic Watchdog Structure in GTDT table of ACPI,
and create a platform device with that information.
This platform device can be used by the ARM SBSA Generic
On Tue, 2015-05-26 at 09:46 +0200, Sascha Hauer wrote:
+static struct clk_onecell_data *mt8173_top_clk_data;
+static struct clk_onecell_data *mt8173_pll_clk_data;
+
+static void mtk_clk_enable_critical(void)
+{
+ if (!mt8173_top_clk_data || !mt8173_pll_clk_data)
+ return;
insert_resource() can fail when the resource added overlaps
(partially or fully) with another.
Device tree and AMBA devices may contain resources that overlap, so they
could not call platform_device_add (see 02bbde7849e6 ('Revert of:
use platform_device_add'))
On the other hand, device trees
of_platform_device_create_pdata() was using of_device_add() to create
the devices, but of_platform_device_destroy was using
platform_device_unregister() to free them.
of_device_add(), do not call insert_resource(), which initializes the
parent field of the resource structure, needed by
platform_device_del only checks the type of the resource in order to
call release_resource.
On the other hand, platform_device_add calls insert_resource for any
resource that has a parent.
Make both code branches balanced.
Signed-off-by: Ricardo Ribalda Delgado ricardo.riba...@gmail.com
---
Failure path of platform_device_add was almost the same as
platform_device_del. Refactor same code in a function.
Acked-by: Rob Herring r...@kernel.org
Signed-off-by: Ricardo Ribalda Delgado ricardo.riba...@gmail.com
---
drivers/base/platform.c | 60
On Thu, May 21, 2015 at 03:12:56PM +0800, James Liao wrote:
Add REF2USB_TX clock support into MT8173 APMIXEDSYS. This clock
is needed by USB 3.0.
+
+static struct clk *mtk_clk_register_ref2usb_tx(const char *name,
+ void __iomem *reg)
+{
+ struct mtk_ref2usb_tx
Hi zhou,
On 05/26/2015 04:49 AM, Zhou Wang wrote:
struct pcie_port {
+#ifdef CONFIG_ARM
+/*
+ * this is a temporary hack to let the driver work on
+ * both arm32 and arm64. it can be removed after the
+ * arm32 cleanup is complete and bios32.c has stopped
+ * referencing
On 22/05/15 17:33, Arnd Bergmann wrote:
On Friday 22 May 2015 16:54:17 Srinivas Kandagatla wrote:
diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig
index 6ecac6c..f50197e 100644
--- a/sound/soc/qcom/Kconfig
+++ b/sound/soc/qcom/Kconfig
@@ -26,7 +26,7 @@ config SND_SOC_LPASS_APQ8016
On Thu, May 21, 2015 at 03:12:54PM +0800, James Liao wrote:
This adds the binding documentation for the mmsys, imgsys, vdecsys,
vencsys and vencltsys controllers found on Mediatek SoCs.
index 000..a5b94a7
--- /dev/null
+++
From: Wei Chen wei.c...@csr.com
The Hardware Spinlock device on atlas7 provides hardware assistance
for synchronization between the multiple processors in the system
(dual Cortex-A7, CAN bus Cortex-M3 and audio DSP).
This patch adds the DT bindings information for this hwspinlock
module.
Cc:
On Tue, 2015-05-26 at 08:05 +0200, Sascha Hauer wrote:
On Thu, May 21, 2015 at 04:22:31PM +0800, YH Huang wrote:
On Mon, 2015-05-18 at 11:42 +0800, Daniel Kurtz wrote:
...
On Mon, May 11, 2015 at 5:26 PM, YH Huang yh.hu...@mediatek.com wrote:
+
+static const struct of_device_id
On Mon, May 25, 2015 at 01:03:54PM +0200, Hauke Mehrtens wrote:
diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c
index 1bed3cb..510fc0d 100644
--- a/arch/mips/jz4740/setup.c
+++ b/arch/mips/jz4740/setup.c
@@ -83,6 +83,9 @@ arch_initcall(populate_machine);
const
of_platform_depopulate can lead to a kernel error when calling
release_resource()
The reason is that it is trying to release a resource that was not allocated
via insert_resource()
of_platform_depopulate()
of_platform_device_destroy()
platform_device_unregister(platform_device
On Tuesday 26 May 2015 10:49:51 Zhou Wang wrote:
I am a little confused that pci_sys_data is still needed as we don't use the
code
in bios32. What was the problem you met? Could you share me more information?
Then
let's see how to solve the problem.
The PCI core code still calls
From: Wei Chen wei.c...@csr.com
This patch moves to use generic dt-binding for hwspinlock providers and
clients.
add #hwlock-cells for the provider and hwlocks for clients.
Cc: Suman Anna s-a...@ti.com
Cc: Bjorn Andersson bj...@kryo.se
Signed-off-by: Wei Chen wei.c...@csr.com
Signed-off-by:
From: Wei Chen wei.c...@csr.com
Add hwspinlock support for the CSR atlas7 SoC.
The Hardware Spinlock device on atlas7 provides hardware assistance
for synchronization between the multiple processors in the system
(dual Cortex-A7, CAN bus Cortex-M3 and audio DSP).
Cc: Suman Anna s-a...@ti.com
Hi Sascha,
On Tue, 2015-05-26 at 09:56 +0200, Sascha Hauer wrote:
On Thu, May 21, 2015 at 03:12:54PM +0800, James Liao wrote:
This adds the binding documentation for the mmsys, imgsys, vdecsys,
vencsys and vencltsys controllers found on Mediatek SoCs.
index 000..a5b94a7
---
On Tue, 26 May 2015 09:06:29 +
Jason Cooper ja...@lakedaemon.net wrote:
On Mon, May 25, 2015 at 08:43:02PM +0200, Boris Brezillon wrote:
Jason, Gregory,
On Mon, 25 May 2015 16:46:51 +
Jason Cooper ja...@lakedaemon.net wrote:
On Mon, May 25, 2015 at 05:39:13PM +0200,
On Mon, May 25, 2015 at 08:43:02PM +0200, Boris Brezillon wrote:
Jason, Gregory,
On Mon, 25 May 2015 16:46:51 +
Jason Cooper ja...@lakedaemon.net wrote:
On Mon, May 25, 2015 at 05:39:13PM +0200, Gregory CLEMENT wrote:
Hi Boris, Arnaud,
On 22/05/2015 15:34, Boris Brezillon
On Mon, 25 May 2015 17:10:37 +0200
Gregory CLEMENT gregory.clem...@free-electrons.com wrote:
Hi Boris,
On 22/05/2015 15:34, Boris Brezillon wrote:
Enable the crypto IP on armada-xp-gp.
Signed-off-by: Boris Brezillon boris.brezil...@free-electrons.com
---
Dear Boris Brezillon,
On Tue, 26 May 2015 11:03:45 +0200, Boris Brezillon wrote:
There is no clocks property. After a quick look on the datasheet, indeed I
didn't
find any clock which match the CESA. In this case you should update the
binding
documentation by adding that the clock is
Hi Gregory,
On Mon, 25 May 2015 17:33:24 +0200
Gregory CLEMENT gregory.clem...@free-electrons.com wrote:
Hi Boris, Arnaud,
On 22/05/2015 15:34, Boris Brezillon wrote:
From: Arnaud Ebalard a...@natisbad.org
Add crypto related nodes in armada-370.dtsi.
Signed-off-by: Arnaud
On Tue, 26 May 2015 10:59:36 +0200, Boris Brezillon
boris.brezil...@free-electrons.com wrote:
snip
As the crypto engine really depend on the SoC itself and not of the
board,
what about updating the dts of the other board using an Armada XP?
But that means introducing changes I haven't
On Tue, May 26, 2015 at 11:10:51AM +0200, Boris Brezillon wrote:
On Tue, 26 May 2015 09:06:29 +
Jason Cooper ja...@lakedaemon.net wrote:
On Mon, May 25, 2015 at 08:43:02PM +0200, Boris Brezillon wrote:
Jason, Gregory,
On Mon, 25 May 2015 16:46:51 +
Jason Cooper
Hi Sascha,
On Tue, 2015-05-26 at 10:05 +0200, Sascha Hauer wrote:
On Thu, May 21, 2015 at 03:12:56PM +0800, James Liao wrote:
+static void __init mtk_clk_register_apmixedsys_special(struct device_node
*node,
+ struct clk_onecell_data *clk_data)
+{
+ void __iomem
On Tue, May 26, 2015 at 05:11:15PM +0800, James Liao wrote:
Hi Sascha,
On Tue, 2015-05-26 at 10:05 +0200, Sascha Hauer wrote:
On Thu, May 21, 2015 at 03:12:56PM +0800, James Liao wrote:
+static void __init mtk_clk_register_apmixedsys_special(struct
device_node *node,
+
On Wed, Apr 15, 2015 at 04:35:15PM +0300, Ivan T. Ivanov wrote:
On recent Qualcomm platforms VBUS and ID lines are not routed to
USB PHY LINK controller. Use extcon framework to receive connect
and disconnect ID and VBUS notification.
Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
---
On Tue, 26 May 2015 11:10:41 +0200
Thomas Petazzoni thomas.petazz...@free-electrons.com wrote:
Dear Boris Brezillon,
On Tue, 26 May 2015 11:03:45 +0200, Boris Brezillon wrote:
There is no clocks property. After a quick look on the datasheet, indeed
I didn't
find any clock which
The commit df59fa7f4bca spi: orion: support armada extended baud
rates was too optimistic for the maximum baud rate that the Armada
SoCs can support. According to the hardware datasheet the maximum
frequency supported by the Armada 370 SoC is tclk/4. But for the
Armada XP, Armada 38x and Armada
The commit df59fa7f4bca spi: orion: support armada extended baud
rates made the assumptions that all the Armada SoCs supported the
same maximum frequency. However, according the hardware datasheet, the
maximum frequency supported by the Armada 370 SoC is tclk/4, for the
Armada XP, Armada 38x and
Use the new compatible introduced in rder to beneficiate of a wider
and more accurate range of baud rates to be used.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/boot/dts/armada-370-xp.dtsi | 2 --
arch/arm/boot/dts/armada-370.dtsi| 4
Hi,
The commit df59fa7f4bca spi: orion: support armada extended baud
rates was too optimistic for the maximum baud rate that the Armada
SoCs can support. Fixing it is the purpose of the 1st patch.
Actually the Armada SoCs do not have the same constraints, some of
them have maximum absolute
Hi Sascha,
On Tue, 2015-05-26 at 11:41 +0200, Sascha Hauer wrote:
On Tue, May 26, 2015 at 05:11:15PM +0800, James Liao wrote:
On Tue, 2015-05-26 at 10:05 +0200, Sascha Hauer wrote:
On Thu, May 21, 2015 at 03:12:56PM +0800, James Liao wrote:
+static void __init
On Tue, May 26, 2015 at 11:44:42AM +0200, Gregory CLEMENT wrote:
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Reported-by: Kostya Porotchkin kos...@marvell.com
Cc: sta...@vger.kernel.org #Fixes df59fa7f4bca
Applied, but please format this stuff in a standard fashion - use
On Tue, May 26, 2015 at 11:44:43AM +0200, Gregory CLEMENT wrote:
The commit df59fa7f4bca spi: orion: support armada extended baud
rates made the assumptions that all the Armada SoCs supported the
same maximum frequency. However, according the hardware datasheet, the
maximum frequency supported
[...]
+{
+ unsigned long tmo = jiffies + msecs_to_jiffies(20);
+
+ while ((readl(host-base + SDC_STS) SDC_STS_CMDBUSY)
+time_before(jiffies, tmo))
+ continue;
+
+ if (readl(host-base + SDC_STS) SDC_STS_CMDBUSY) {
On 21 May 2015 at 10:43, Suman Tripathi stripa...@apm.com wrote:
The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk.
This patch adds the support to disable SDR104/SDR50/DDR50 based on
reading the capability register 0.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
---
Hi Paul,
this patch is also for omap2... Can you review it too?
On Saturday 28 February 2015 17:24:36 Pavel Machek wrote:
On Thu 2015-02-26 14:49:52, Pali Rohár wrote:
Register crypto hwmod links only if they are not disabled in DT.
If DT information is missing, enable them only for GP
Add a device tree node for the On-Chip One Time Programmable
Controller (OCOTP) and the On-Chip ROM.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/boot/dts/vfxxx.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/vfxxx.dtsi
--- a/Documentation/devicetree/bindings/spi/spi-orion.txt
+++ b/Documentation/devicetree/bindings/spi/spi-orion.txt
@@ -1,7 +1,13 @@
Marvell Orion SPI device
Required properties:
-- compatible : should be marvell,orion-spi or marvell,armada-370-spi.
+- compatible : should be on of the
Hello,
This patchset implements SoC bus support for Freescale Vybrid platform,
implementing the following
https://www.kernel.org/doc/Documentation/ABI/testing/sysfs-devices-soc
and is the third revision.
Version 3 of the patchset can be found here
On Tue, May 26, 2015 at 11:22:45AM +0200, Imre Kaloz wrote:
On Tue, 26 May 2015 10:59:36 +0200, Boris Brezillon
boris.brezil...@free-electrons.com wrote:
snip
As the crypto engine really depend on the SoC itself and not of
the board,
what about updating the dts of the other board using
Hi Pantelis,
On 25/05/15 17:51, Pantelis Antoniou wrote:
Hi Srinivas,
On May 21, 2015, at 19:42 , Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
Thankyou all for providing inputs and comments on previous versions of this
patchset.
Here is the v5 of the patchset addressing all
On Tue, May 26, 2015 at 04:55:36PM +0800, James Liao wrote:
Hi Sascha,
On Tue, 2015-05-26 at 09:56 +0200, Sascha Hauer wrote:
On Thu, May 21, 2015 at 03:12:54PM +0800, James Liao wrote:
This adds the binding documentation for the mmsys, imgsys, vdecsys,
vencsys and vencltsys
This adds a SoC driver to be used by the Freescale Vybrid SoC's.
We create the fsl directory for holding the different Freescale
designs. Driver utilises syscon to get the various register values
needed. After this sysfs exposes some SoC specific properties as
below:
cd /sys/devices/soc0
ls
clocksource: sti: Provide support for the ST LPC Clocksource IP
This IP is shared with Watchdog and RTC functionality. All 3 of
these devices are mutually exclusive from one another i.e. Only 1
IP can be used at any given time. We use the device-driver model
combined with a DT 'mode' property
On 05/26/2015 03:28 AM, Barry Song wrote:
From: Wei Chen wei.c...@csr.com
The Hardware Spinlock device on atlas7 provides hardware assistance
for synchronization between the multiple processors in the system
(dual Cortex-A7, CAN bus Cortex-M3 and audio DSP).
This patch adds the DT bindings
Hi Srinivas,
On May 26, 2015, at 12:12 , Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
Hi Pantelis,
On 25/05/15 17:51, Pantelis Antoniou wrote:
Hi Srinivas,
On May 21, 2015, at 19:42 , Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
Thankyou all for
The purpose of this patchset is to support CPUFreq on Pistachio SoC.
However, given Pistachio uses the MIPS GIC clocksource and clockevent
drivers (clocked from the CPU), adding CPUFreq support needs some work.
This patchset changes the MIPS GIC clockevent driver to update
the frequency of the
This commit introduces a new config, so the user can choose to enable
the General Purpose Timer based clocksource. This option is required
to have CPUFreq support.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@imgtec.com
---
arch/mips/Kconfig | 1 +
arch/mips/pistachio/Kconfig | 13
This commit adds the required checks on the functions that return
an error. Some of them are not critical, so only a warning is
printed.
Reviewed-by: Andrew Bresticker abres...@chromium.org
Signed-off-by: Ezequiel Garcia ezequiel.gar...@imgtec.com
---
drivers/clocksource/mips-gic-timer.c | 16
On 05/26/2015 03:28 AM, Barry Song wrote:
From: Wei Chen wei.c...@csr.com
Add hwspinlock support for the CSR atlas7 SoC.
The Hardware Spinlock device on atlas7 provides hardware assistance
for synchronization between the multiple processors in the system
(dual Cortex-A7, CAN bus Cortex-M3
This commit introduces the clockevent frequency update, using
a clock notifier. It will be used to support CPUFreq on platforms
using MIPS GIC based clockevents.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@imgtec.com
---
drivers/clocksource/mips-gic-timer.c | 31
The Pistachio SoC provides four general purpose timers, and allow
to implement a clocksource driver.
This driver can be used as a replacement for the MIPS GIC and MIPS R4K
clocksources and sched clocks, which are clocked from the CPU clock.
Given the general purpose timers are clocked from an
Add a device-tree binding document for the clocksource driver provided
by Pistachio SoC general purpose timers.
Reviewed-by: Andrew Bresticker abres...@chromium.org
Signed-off-by: Ezequiel Garcia ezequiel.gar...@imgtec.com
---
.../bindings/timer/img,pistachio-gptimer.txt | 28
On Tue, May 26, 2015 at 11:35:19AM -0500, Timur Tabi wrote:
On 05/26/2015 03:28 AM, Hanjun Guo wrote:
early_acpi_os_unmap_memory((char *)table, tbl_size);
}
please add
#ifdef CONFIG_ARM_SBSA_WATCHDOG
(acpi gtdt code)
#endif
I don't agree with this. The GTDT should be
This is preparation work for the introduction of clockevent frequency
update with a clock notifier. This is only possible when the device
is passed a clk struct, so let's split the legacy and devicetree
initialization.
Reviewed-by: Andrew Bresticker abres...@chromium.org
Signed-off-by: Ezequiel
For the clock to be used (e.g. get its rate through clk_get_rate)
it should be prepared and enabled first.
Also, while the clock is enabled the driver must hold a reference to it,
so let's remove the call to clk_put.
Reviewed-by: Andrew Bresticker abres...@chromium.org
Signed-off-by: Ezequiel
On 26 May 2015 at 23:36, Guenter Roeck li...@roeck-us.net wrote:
On Tue, May 26, 2015 at 04:18:42PM +0100, Will Deacon wrote:
On Tue, May 26, 2015 at 04:02:56PM +0100, Ashwin Chaugule wrote:
On 26 May 2015 at 08:28, Will Deacon will.dea...@arm.com wrote:
On Mon, May 25, 2015 at 11:03:13AM
Hi Jassi,
On Mon, May 11, 2015 at 8:56 PM, Jassi Brar jassisinghb...@gmail.com wrote:
Applied patches 2, 3, 6 7
Please drop patches 6 and 7. Lee Jones has NAK'ed the MFD driver, so
I'll have to re-spin this series without using an MFD.
Thanks,
andrew
--
To unsubscribe from this list: send
From: Frank Li frank...@freescale.com
enable snvs ONOFF power key support
Signed-off-by: Frank Li frank...@freescale.com
---
arch/arm/boot/dts/imx6sx.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index
Hi Daniel,
2015-05-22 22:41 GMT+02:00 Daniel Thompson daniel.thomp...@linaro.org:
2. Allocating ~80 clock components appears to fragment memory enough
to prevent busybox (.text is ~300K, non-XIP) from running getty.
I have to use init=/bin/sh to avoid OOM problems.
Yes, I reproduced
On Fri, Mar 20, 2015 at 08:11:15PM +0100, Hans de Goede wrote:
This is based on initial code to get the Allwinner sunxi musb controller
supported by Chen-Yu Tsai and Roman Byshko.
This adds support for the Allwinner sunxi musb controller in both host only
and otg mode. Peripheral only mode
On Tue, 19 May 2015, S Twiss wrote:
From: S Twiss stwiss.opensou...@diasemi.com
Add MFD core driver support for DA9062
Signed-off-by: Steve Twiss stwiss.opensou...@diasemi.com
---
Changes in V3:
- Removed references to the RTC and OnKey in the mfd_cell definition.
Changes in V2:
On Mon, May 25, 2015 at 12:04 PM, Sören Brinkmann
soren.brinkm...@xilinx.com wrote:
On Fri, 2015-05-22 at 07:43AM +0200, Michal Simek wrote:
On 05/22/2015 01:37 AM, Moritz Fischer wrote:
Signed-off-by: Moritz Fischer moritz.fisc...@ettus.com
---
.../bindings/mailbox/xilinx-mailbox.txt
On Mon, May 25, 2015 at 6:56 AM, Jingoo Han jingooh...@gmail.com wrote:
On Monday, May 25, 2015 3:05 PM, Michal Simek wrote:
On 05/22/2015 08:03 PM, Moritz Fischer wrote:
This patchset adds mailbox framework integration for the Xilinx LogiCORE IP
mailbox. The Xilinx LogiCORE IP mailbox is a
On 26 May 2015 at 11:18, Will Deacon will.dea...@arm.com wrote:
On Tue, May 26, 2015 at 04:02:56PM +0100, Ashwin Chaugule wrote:
On 26 May 2015 at 08:28, Will Deacon will.dea...@arm.com wrote:
On Mon, May 25, 2015 at 11:03:13AM +0100, fu@linaro.org wrote:
From: Fu Wei fu@linaro.org
On Tue, May 26, 2015 at 04:18:42PM +0100, Will Deacon wrote:
On Tue, May 26, 2015 at 04:02:56PM +0100, Ashwin Chaugule wrote:
On 26 May 2015 at 08:28, Will Deacon will.dea...@arm.com wrote:
On Mon, May 25, 2015 at 11:03:13AM +0100, fu@linaro.org wrote:
From: Fu Wei fu@linaro.org
On Sun, Mar 29, 2015 at 12:50:46PM +0200, Hans de Goede wrote:
The sunxi otg phy has a bug where it wrongly detects a high speed squelch
when reset on the root port gets de-asserted with a lo-speed device.
The workaround for this is to disable squelch detect before de-asserting
reset, and
Sorry for delays, nothing new inside, all stuff that was noted
previously now fixed.
Andrew Andrianov (1):
ARM: mvebu: dts: Add dts file for DLink DNS-327L
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/armada-370-dlink-dns327l.dts | 357 +
DNS-327L is a 2-bay NAS with the following specs:
- 512MiB RAM
- 128MiB NAND Flash
- 1 GbE interface (Marvell PHY)
- 1 rear USB 3.0 port (via PCIe USB 3.0 controller)
- 2 internal SATA ports handled by the Armada 370:
uses 2 gpios for power control
- two
From: Dinh Nguyen dingu...@opensource.altera.com
Update the arria10 gmac nodes with all the necessary properties for ethernet
to function on the Arria10 devkit.
Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 11 +++
Hi,
On 05/26/2015 05:48 PM, Felipe Balbi wrote:
On Fri, Mar 20, 2015 at 08:11:15PM +0100, Hans de Goede wrote:
This is based on initial code to get the Allwinner sunxi musb controller
supported by Chen-Yu Tsai and Roman Byshko.
This adds support for the Allwinner sunxi musb controller in both
From: Robin Gong b38...@freescale.com
add snvs power key driver.
It work in imx chips after i.mx6sx
ON/OFF key used power on/off whole system.
This driver make it wakeup from suspend state when short press
ON/OFF key.
Long time press will trig SNVS power off chip without software
intervention.
From: Frank Li frank...@freescale.com
snvs included rtc, on/off key, power-off module
change to syscon to access register
Signed-off-by: Frank Li frank...@freescale.com
---
drivers/rtc/rtc-snvs.c | 132 +
1 file changed, 67 insertions(+), 65
From: Frank Li frank...@freescale.com
snvs actually is multi fucntion driver.
Change to use syscon to access register.
Change snvs parent interrupt to option because single function
may have seperated irq number.
Signed-off-by: Frank Li frank...@freescale.com
---
From: Frank Li frank...@freescale.com
snvs is MFP device. Change dts to use syscon to allocate register resource.
snvs power off also switch to common syscon-poweroff
Signed-off-by: Frank Li frank...@freescale.com
---
arch/arm/boot/dts/imx6qdl.dtsi | 21 +++--
From: Frank Li frank...@freescale.com
Tested old and new dts in imx6sx platform.
Change from v5 to v6
- use dev_warn and dev_err
- use phandle regmap
- update document and dts for phandle regmap
- use data variable in rtc-snvs.c
Change from v3 to v4
- fix align
- change to pr_warn
Change
From: Frank Li frank...@freescale.com
The snvs-pwrkey is designed to enable POWER key function which controlled
by SNVS ONOFF. the driver can report the status of POWER key and wakeup
system if pressed after system suspend.
Signed-off-by: Frank Li frank...@freescale.com
Signed-off-by: Robin Gong
On 24 May 2015 at 20:32, Hauke Mehrtens ha...@hauke-m.de wrote:
This adds the NAND flash chip description for a standard chip found
connected to this SoC. This makes use of generic Broadcom NAND driver
with the iProc interface.
I still wait/hope for Brian's reply in
[PATCH 5/7] mtd: brcmnand:
Switch to use ma_request_slave_channel_compat_reason() to request the DMA
channels. Only fall back to pio mode if the error code returned is not
-EPROBE_DEFER, otherwise return from the probe with the -EPROBE_DEFER.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
CC: Ulf Hansson
Switch to use ma_request_slave_channel_compat_reason() to request the DMA
channels. Only fall back to pio mode if the error code returned is not
-EPROBE_DEFER, otherwise return from the probe with the -EPROBE_DEFER.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
CC: Herbert Xu
dma_request_slave_channel_compat() 'eats' up the returned error codes which
prevents drivers using the compat call to be able to do deferred probing.
The new wrapper is identical in functionality but it will return with error
code in case of failure and will pass the -EPROBE_DEFER to the caller
The driver will not probe without valid DMA channels so no need to check
if they are valid when the module is removed.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
CC: Ulf Hansson ulf.hans...@linaro.org
---
drivers/mmc/host/omap_hsmmc.c | 6 ++
1 file changed, 2 insertions(+), 4
Hi Andrew, Mark,
On 26/05/2015 14:08, Andrew Lunn wrote:
--- a/Documentation/devicetree/bindings/spi/spi-orion.txt
+++ b/Documentation/devicetree/bindings/spi/spi-orion.txt
@@ -1,7 +1,13 @@
Marvell Orion SPI device
Required properties:
-- compatible : should be marvell,orion-spi or
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